version 1.12, 2004/12/19 13:26:48 |
version 1.13, 2007/10/17 02:30:23 |
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/* $OpenBSD$ */ |
/* $OpenBSD$ */ |
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/* |
/* |
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* Copyright (c) 2007 Mike Belopuhov, Aleksey Lomovtsev |
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* |
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* Permission to use, copy, modify, and distribute this software for any |
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* purpose with or without fee is hereby granted, provided that the above |
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* copyright notice and this permission notice appear in all copies. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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*/ |
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/* |
* Pentium performance counter control program for OpenBSD. |
* Pentium performance counter control program for OpenBSD. |
* Copyright 1996 David Mazieres <dm@lcs.mit.edu>. |
* Copyright 1996 David Mazieres <dm@lcs.mit.edu>. |
* |
* |
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* OpenBSD project by leaving this copyright notice intact. |
* OpenBSD project by leaving this copyright notice intact. |
*/ |
*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <unistd.h> |
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#include <sys/param.h> |
#include <sys/param.h> |
#include <sys/types.h> |
#include <sys/types.h> |
#include <sys/stat.h> |
#include <sys/stat.h> |
#include <sys/sysctl.h> |
#include <sys/sysctl.h> |
#include <sys/ioctl.h> |
#include <sys/ioctl.h> |
#include <err.h> |
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#include <fcntl.h> |
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#include <machine/cpu.h> |
#include <machine/cpu.h> |
#include <machine/pctr.h> |
#include <machine/pctr.h> |
#include <machine/specialreg.h> |
#include <machine/specialreg.h> |
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#define CFL_MESI 0x1 /* Unit mask accepts MESI encoding */ |
#include <errno.h> |
#define CFL_SA 0x2 /* Unit mask accepts Self/Any bit */ |
#include <err.h> |
#define CFL_C0 0x4 /* Counter 0 only */ |
#include <fcntl.h> |
#define CFL_C1 0x8 /* Counter 1 only */ |
#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <sysexits.h> |
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#include <unistd.h> |
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/* Kernel cpuid values. */ |
#include "pctrvar.h" |
int cpu_id, cpu_feature; |
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char cpu_vendor[16]; |
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int pctr_isintel; |
static int cpu_type; |
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static int tsc_avail; |
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#define usetsc (cpu_feature & CPUID_TSC) |
static int ctr, func, masku, thold; |
#define usep5ctr (pctr_isintel && (((cpu_id >> 8) & 15) == 5) && \ |
static int cflag, eflag, iflag, kflag, uflag; |
(((cpu_id >> 4) & 15) > 0)) |
static int Mflag, Eflag, Sflag, Iflag, Aflag; |
#define usep6ctr (pctr_isintel && ((cpu_id >> 8) & 15) == 6) |
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#define cpufamily ((cpu_id >> 8) & 15) |
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extern char *__progname; |
static int pctr_cpu_creds(void); |
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static char *pctr_fn2str(u_int32_t); |
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static void pctr_printvals(struct pctrst *); |
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static int pctr_read(struct pctrst *); |
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static int pctr_write(int, u_int32_t); |
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static void pctr_list_fnct(void); |
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static int pctr_set_cntr(void); |
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static void usage(void); |
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struct ctrfn { |
int |
u_int fn; |
main(int argc, char **argv) |
int flags; |
{ |
char *name; |
const char *errstr; |
char *desc; |
struct pctrst st; |
}; |
int ch = -1; |
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int list_mode = 0, set_mode = 0; |
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struct ctrfn p5fn[] = { |
if (pctr_cpu_creds()) |
{0x00, 0, "Data read", NULL}, |
errx(1, "pctr is only supported on i386 and amd64 " |
{0x01, 0, "Data write", NULL}, |
"architectures by now"); |
{0x02, 0, "Data TLB miss", NULL}, |
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{0x03, 0, "Data read miss", NULL}, |
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{0x04, 0, "Data write miss", NULL}, |
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{0x05, 0, "Write (hit) to M or E state lines", NULL}, |
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{0x06, 0, "Data cache lines written back", NULL}, |
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{0x07, 0, "Data cache snoops", NULL}, |
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{0x08, 0, "Data cache snoop hits", NULL}, |
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{0x09, 0, "Memory accesses in both pipes", NULL}, |
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{0x0a, 0, "Bank conflicts", NULL}, |
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{0x0b, 0, "Misaligned data memory references", NULL}, |
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{0x0c, 0, "Code read", NULL}, |
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{0x0d, 0, "Code TLB miss", NULL}, |
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{0x0e, 0, "Code cache miss", NULL}, |
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{0x0f, 0, "Any segment register load", NULL}, |
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{0x12, 0, "Branches", NULL}, |
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{0x13, 0, "BTB hits", NULL}, |
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{0x14, 0, "Taken branch or BTB hit", NULL}, |
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{0x15, 0, "Pipeline flushes", NULL}, |
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{0x16, 0, "Instructions executed", NULL}, |
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{0x17, 0, "Instructions executed in the V-pipe", NULL}, |
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{0x18, 0, "Bus utilization (clocks)", NULL}, |
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{0x19, 0, "Pipeline stalled by write backup", NULL}, |
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{0x1a, 0, "Pipeline stalled by data memory read", NULL}, |
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{0x1b, 0, "Pipeline stalled by write to E or M line", NULL}, |
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{0x1c, 0, "Locked bus cycle", NULL}, |
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{0x1d, 0, "I/O read or write cycle", NULL}, |
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{0x1e, 0, "Noncacheable memory references", NULL}, |
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{0x1f, 0, "AGI (Address Generation Interlock)", NULL}, |
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{0x22, 0, "Floating-point operations", NULL}, |
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{0x23, 0, "Breakpoint 0 match", NULL}, |
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{0x24, 0, "Breakpoint 1 match", NULL}, |
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{0x25, 0, "Breakpoint 2 match", NULL}, |
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{0x26, 0, "Breakpoint 3 match", NULL}, |
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{0x27, 0, "Hardware interrupts", NULL}, |
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{0x28, 0, "Data read or data write", NULL}, |
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{0x29, 0, "Data read miss or data write miss", NULL}, |
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{0x0, 0, NULL, NULL}, |
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}; |
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struct ctrfn p6fn[] = { |
while ((ch = getopt(argc, argv, "cef:iklm:s:t:uMESIA")) != -1) |
{0x03, 0, "LD_BLOCKS", |
switch (ch) { |
"Number of store buffer blocks."}, |
case 'l': |
{0x04, 0, "SB_DRAINS", |
list_mode++; |
"Number of store buffer drain cycles."}, |
break; |
{0x05, 0, "MISALIGN_MEM_REF", |
case 's': |
"Number of misaligned data memory references."}, |
set_mode++; |
{0x06, 0, "SEGMENT_REG_LOADS", |
ctr = strtonum(optarg, 0, PCTR_NUM-1, &errstr); |
"Number of segment register loads."}, |
if (errstr) |
{0x10, CFL_C0, "FP_COMP_OPS_EXE", |
errx(1, "counter number is %s: %s", errstr, |
"Number of computational floating-point operations executed."}, |
optarg); |
{0x11, CFL_C1, "FP_ASSIST", |
break; |
"Number of floating-point exception cases handled by microcode."}, |
case 'f': |
{0x12, CFL_C1, "MUL", |
if (sscanf(optarg, "%x", &func) <= 0 || func < 0 || |
"Number of multiplies."}, |
func > PCTR_MAX_FUNCT) |
{0x13, CFL_C1, "DIV", |
errx(1, "invalid function number"); |
"Number of divides."}, |
break; |
{0x14, CFL_C0, "CYCLES_DIV_BUSY", |
case 'm': |
"Number of cycles during which the divider is busy."}, |
if (sscanf(optarg, "%x", &masku) <= 0 || masku < 0 || |
{0x21, 0, "L2_ADS", |
masku > PCTR_MAX_UMASK) |
"Number of L2 address strobes."}, |
errx(1, "invalid unit mask number"); |
{0x22, 0, "L2_DBUS_BUSY", |
break; |
"Number of cycles durring which the data bus was busy."}, |
case 't': |
{0x23, 0, "L2_DBUS_BUSY_RD", |
thold = strtonum(optarg, 0, 0xff, &errstr); |
"Number of cycles during which the data bus was busy transferring " |
if (errstr) |
"data from L2 to the processor."}, |
errx(1, "threshold is %s: %s", errstr, optarg); |
{0x24, 0, "L2_LINES_IN", |
break; |
"Number of lines allocated in the L2."}, |
/* flags */ |
{0x25, 0, "L2_M_LINES_INM", |
case 'c': |
"Number of modified lines allocated in the L2."}, |
cflag++; |
{0x26, 0, "L2_LINES_OUT", |
break; |
"Number of lines removed from the L2 for any reason."}, |
case 'e': |
{0x27, 0, "L2_M_LINES_OUTM", |
eflag++; |
"Number of modified lines removed from the L2 for any reason."}, |
break; |
{0x28, CFL_MESI, "L2_IFETCH", |
case 'i': |
"Number of L2 instruction fetches."}, |
iflag++; |
{0x29, CFL_MESI, "L2_LD", |
break; |
"Number of L2 data loads."}, |
case 'k': |
{0x2a, CFL_MESI, "L2_ST", |
kflag++; |
"Number of L2 data stores."}, |
break; |
{0x2e, CFL_MESI, "L2_RQSTS", |
case 'u': |
"Number of L2 requests."}, |
uflag++; |
{0x43, 0, "DATA_MEM_REFS", |
break; |
"All memory references, both cacheable and non-cacheable."}, |
/* MESI/A flags */ |
{0x45, 0, "DCU_LINES_IN", |
case 'M': |
"Total lines allocated in the DCU."}, |
if (Aflag) |
{0x46, 0, "DCU_M_LINES_IN", |
errx(1, "M, E, S, I and A are mutually " |
"Number of M state lines allocated in the DCU."}, |
"exclusive"); |
{0x47, 0, "DCU_M_LINES_OUT", |
Mflag++; |
"Number of M state lines evicted from the DCU. " |
break; |
"This includes evictions via snoop HITM, intervention or replacement"}, |
case 'E': |
{0x48, 0, "DCU_MISS_OUTSTANDING", |
if (Aflag) |
"Weighted number of cycles while a DCU miss is outstanding."}, |
errx(1, "M, E, S, I and A are mutually " |
{0x60, 0, "BUS_REQ_OUTSTANDING", |
"exclusive"); |
"Number of bus requests outstanding."}, |
Eflag++; |
{0x61, 0, "BUS_BNR_DRV", |
break; |
"Number of bus clock cycles during which the processor is " |
case 'S': |
"driving the BNR pin."}, |
if (Aflag) |
{0x62, CFL_SA, "BUS_DRDY_CLOCKS", |
errx(1, "M, E, S, I and A are mutually " |
"Number of clocks during which DRDY is asserted."}, |
"exclusive"); |
{0x63, CFL_SA, "BUS_LOCK_CLOCKS", |
Sflag++; |
"Number of clocks during which LOCK is asserted."}, |
break; |
{0x64, 0, "BUS_DATA_RCV", |
case 'I': |
"Number of bus clock cycles during which the processor is " |
if (Aflag) |
"receiving data."}, |
errx(1, "M, E, S, I and A are mutually " |
{0x65, CFL_SA, "BUS_TRAN_BRD", |
"exclusive"); |
"Number of burst read transactions."}, |
Iflag++; |
{0x66, CFL_SA, "BUS_TRAN_RFO", |
break; |
"Number of read for ownership transactions."}, |
case 'A': |
{0x67, CFL_SA, "BUS_TRANS_WB", |
if (Mflag || Eflag || Sflag || Iflag) |
"Number of write back transactions."}, |
errx(1, "M, E, S, I and A are mutually " |
{0x68, CFL_SA, "BUS_TRAN_IFETCH", |
"exclusive"); |
"Number of instruction fetch transactions."}, |
Aflag++; |
{0x69, CFL_SA, "BUS_TRAN_INVAL", |
break; |
"Number of invalidate transactions."}, |
default: |
{0x6a, CFL_SA, "BUS_TRAN_PWR", |
usage(); |
"Number of partial write transactions."}, |
/* NOTREACHED */ |
{0x6b, CFL_SA, "BUS_TRANS_P", |
} |
"Number of partial transactions."}, |
argc -= optind; |
{0x6c, CFL_SA, "BUS_TRANS_IO", |
argv += optind; |
"Number of I/O transactions."}, |
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{0x6d, CFL_SA, "BUS_TRAN_DEF", |
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"Number of deferred transactions."}, |
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{0x6e, CFL_SA, "BUS_TRAN_BURST", |
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"Number of burst transactions."}, |
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{0x6f, CFL_SA, "BUS_TRAN_MEM", |
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"Number of memory transactions."}, |
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{0x70, CFL_SA, "BUS_TRAN_ANY", |
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"Number of all transactions."}, |
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{0x79, 0, "CPU_CLK_UNHALTED", |
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"Number of cycles during which the processor is not halted."}, |
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{0x7a, 0, "BUS_HIT_DRV", |
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"Number of bus clock cycles during which the processor is " |
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"driving the HIT pin."}, |
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{0x7b, 0, "BUS_HITM_DRV", |
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"Number of bus clock cycles during which the processor is " |
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"driving the HITM pin."}, |
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{0x7e, 0, "BUS_SNOOP_STALL", |
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"Number of clock cycles during which the bus is snoop stalled."}, |
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{0x80, 0, "IFU_IFETCH", |
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"Number of instruction fetches, both cacheable and non-cacheable."}, |
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{0x81, 0, "IFU_IFETCH_MISS", |
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"Number of instruction fetch misses."}, |
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{0x85, 0, "ITLB_MISS", |
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"Number of ITLB misses."}, |
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{0x86, 0, "IFU_MEM_STALL", |
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"Number of cycles that the instruction fetch pipe stage is stalled, " |
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"including cache mises, ITLB misses, ITLB faults, " |
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"and victim cache evictions"}, |
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{0x87, 0, "ILD_STALL", |
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"Number of cycles that the instruction length decoder is stalled"}, |
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{0xa2, 0, "RESOURCE_STALLS", |
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"Number of cycles during which there are resource-related stalls."}, |
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{0xc0, 0, "INST_RETIRED", |
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"Number of instructions retired."}, |
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{0xc1, CFL_C0, "FLOPS", |
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"Number of computational floating-point operations retired."}, |
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{0xc2, 0, "UOPS_RETIRED", |
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"Number of UOPs retired."}, |
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{0xc4, 0, "BR_INST_RETIRED", |
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"Number of branch instructions retired."}, |
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{0xc5, 0, "BR_MISS_PRED_RETIRED", |
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"Number of mispredicted branches retired."}, |
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{0xc6, 0, "CYCLES_INT_MASKED", |
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"Number of processor cycles for which interrupts are disabled."}, |
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{0xc7, 0, "CYCLES_INT_PENDING_AND_MASKED", |
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"Number of processor cycles for which interrupts are disabled " |
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"and interrupts are pending."}, |
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{0xc8, 0, "HW_INT_RX", |
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"Number of hardware interrupts received."}, |
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{0xc9, 0, "BR_TAKEN_RETIRED", |
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"Number of taken branches retired."}, |
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{0xca, 0, "BR_MISS_PRED_TAKEN_RET", |
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"Number of taken mispredictioned branches retired."}, |
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{0xd0, 0, "INST_DECODER", |
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"Number of instructions decoded."}, |
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{0xd2, 0, "PARTIAL_RAT_STALLS", |
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"Number of cycles or events for partial stalls."}, |
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{0xe0, 0, "BR_INST_DECODED", |
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"Number of branch instructions decoded."}, |
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{0xe2, 0, "BTB_MISSES", |
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"Number of branches that miss the BTB."}, |
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{0xe4, 0, "BR_BOGUS", |
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"Number of bogus branches."}, |
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{0xe6, 0, "BACLEARS", |
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"Number of times BACLEAR is asserted."}, |
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{0x0, 0, NULL, NULL}, |
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}; |
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if (list_mode) |
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pctr_list_fnct(); |
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else if (set_mode) { |
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if (pctr_set_cntr() < 0) |
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err(1, "pctr_set_cntr"); |
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} else { |
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bzero(&st, sizeof(st)); |
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if (pctr_read(&st) < 0) |
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err(1, "pctr_read"); |
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pctr_printvals(&st); |
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} |
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return (0); |
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} |
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static int |
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pctr_cpu_creds(void) |
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{ |
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int atype; |
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char arch[16], vendor[64]; |
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int mib[2], cpu_id, cpu_feature; |
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size_t len; |
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/* Get the architecture */ |
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mib[0] = CTL_HW; |
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mib[1] = HW_MACHINE; |
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len = sizeof(arch) - 1; |
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bzero(arch, sizeof(arch)); |
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if (sysctl(mib, 2, arch, &len, NULL, 0) == -1) |
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err(1, "HW_MACHINE"); |
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arch[len] = '\0'; |
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if (strcmp(arch, "i386") == 0) |
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atype = ARCH_I386; |
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else if (strcmp(arch, "amd64") == 0) |
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atype = ARCH_AMD64; |
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else |
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return (EX_UNAVAILABLE); /* unsupported arch */ |
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/* Get the CPU id */ |
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mib[0] = CTL_MACHDEP; |
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mib[1] = CPU_CPUID; |
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len = sizeof(cpu_id); |
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if (sysctl(mib, 2, &cpu_id, &len, NULL, 0) == -1) |
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err(1, "CPU_CPUID"); |
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/* Get the CPU features */ |
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mib[1] = CPU_CPUFEATURE; |
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len = sizeof(cpu_feature); |
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if (sysctl(mib, 2, &cpu_feature, &len, NULL, 0) == -1) |
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err(1, "CPU_CPUFEATURE"); |
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/* Get the processor vendor */ |
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mib[0] = CTL_MACHDEP; |
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mib[1] = CPU_CPUVENDOR; |
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len = sizeof(vendor) - 1; |
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bzero(vendor, sizeof(vendor)); |
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if (sysctl(mib, 2, vendor, &len, NULL, 0) == -1) |
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err(1, "CPU_CPUVENDOR"); |
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vendor[len] = '\0'; |
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switch (atype) { |
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case ARCH_I386: |
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if (strcmp(vendor, "AuthenticAMD") == 0) { |
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if (((cpu_id >> 8) & 15) >= 6) |
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cpu_type = CPU_AMD; |
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else |
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cpu_type = CPU_UNDEF; /* old AMD cpu */ |
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} else if (strcmp(vendor, "GenuineIntel") == 0) { |
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if (((cpu_id >> 8) & 15) == 6 && |
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((cpu_id >> 4) & 15) > 14) |
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cpu_type = CPU_CORE; |
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else if (((cpu_id >> 8) & 15) >= 6) |
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cpu_type = CPU_P6; |
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else if (((cpu_id >> 4) & 15) > 0) |
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cpu_type = CPU_P5; |
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else |
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cpu_type = CPU_UNDEF; /* old Intel cpu */ |
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} |
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if (cpu_feature & CPUID_TSC) |
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tsc_avail = 1; |
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break; |
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case ARCH_AMD64: |
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if (strcmp(vendor, "AuthenticAMD") == 0) |
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cpu_type = CPU_AMD; |
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else if (strcmp(vendor, "GenuineIntel") == 0) |
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cpu_type = CPU_CORE; |
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if (cpu_feature & CPUID_TSC) |
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tsc_avail = 1; |
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break; |
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} |
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return (0); |
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} |
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static __inline int |
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pctr_ctrfn_index(struct ctrfn *cfnp, u_int32_t func) |
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{ |
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int i; |
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for (i = 0; cfnp[i].name != NULL; i++) |
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if (cfnp[i].fn == func) |
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return (i); |
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return (-1); |
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} |
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static char * |
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pctr_fn2str(u_int32_t sel) |
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{ |
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static char buf[128]; |
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struct ctrfn *cfnp = NULL; |
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char th[6], um[5], *msg; |
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u_int32_t fn; |
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int ind; |
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bzero(buf, sizeof(buf)); |
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bzero(th, sizeof(th)); |
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bzero(um, sizeof(um)); |
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switch (cpu_type) { |
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case CPU_P5: |
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fn = sel & 0x3f; |
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if ((ind = pctr_ctrfn_index(p5fn, fn)) < 0) |
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msg = "unknown function"; |
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else |
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msg = p5fn[ind].name; |
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snprintf(buf, sizeof(buf), "%c%c%c %02x %s", |
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sel & PCTR_P5_C ? 'c' : '-', |
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sel & PCTR_P5_U ? 'u' : '-', |
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sel & PCTR_P5_K ? 'k' : '-', |
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fn, msg); |
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break; |
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case CPU_P6: |
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cfnp = p6fn; |
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case CPU_CORE: |
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cfnp = corefn; |
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fn = sel & 0xff; |
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if ((ind = pctr_ctrfn_index(cfnp, fn)) < 0) |
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msg = "unknown function"; |
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else |
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msg = cfnp[ind].name; |
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if (cfnp[ind].name && cfnp[ind].flags & CFL_MESI) |
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snprintf(um, sizeof (um), "%c%c%c%c", |
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sel & PCTR_X86_UM_M ? 'M' : '-', |
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sel & PCTR_X86_UM_E ? 'E' : '-', |
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sel & PCTR_X86_UM_S ? 'S' : '-', |
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sel & PCTR_X86_UM_I ? 'I' : '-'); |
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else if (cfnp[ind].name && cfnp[ind].flags & CFL_SA) |
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snprintf(um, sizeof(um), "%c", |
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sel & PCTR_X86_UM_A ? 'A' : '-'); |
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if (sel >> PCTR_X86_CM_SHIFT) |
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snprintf(th, sizeof(th), "+%d", |
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sel >> PCTR_X86_CM_SHIFT); |
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snprintf(buf, sizeof(buf), "%c%c%c%c %02x %02x %s %s %s", |
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sel & PCTR_X86_I ? 'i' : '-', |
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sel & PCTR_X86_E ? 'e' : '-', |
|
sel & PCTR_X86_K ? 'k' : '-', |
|
sel & PCTR_X86_U ? 'u' : '-', |
|
fn, (sel >> PCTR_X86_UM_SHIFT) & 0xff, th, um, msg); |
|
break; |
|
|
|
break; |
|
case CPU_AMD: |
|
fn = sel & 0xff; |
|
if (sel >> PCTR_X86_CM_SHIFT) |
|
snprintf(th, sizeof(th), "+%d", |
|
sel >> PCTR_X86_CM_SHIFT); |
|
snprintf(buf, sizeof(buf), "%c%c%c%c %02x %02x %s", |
|
sel & PCTR_X86_I ? 'i' : '-', |
|
sel & PCTR_X86_E ? 'e' : '-', |
|
sel & PCTR_X86_K ? 'k' : '-', |
|
sel & PCTR_X86_U ? 'u' : '-', |
|
fn, (sel >> PCTR_X86_UM_SHIFT) & 0xff, th); |
|
break; |
|
} |
|
return (buf); |
|
} |
|
|
static void |
static void |
printdesc(char *desc) |
pctr_printvals(struct pctrst *st) |
{ |
{ |
|
int i, n; |
|
|
|
switch (cpu_type) { |
|
case CPU_P5: |
|
case CPU_P6: |
|
case CPU_CORE: |
|
n = PCTR_INTEL_NUM; |
|
case CPU_AMD: |
|
if (cpu_type == CPU_AMD) |
|
n = PCTR_AMD_NUM; |
|
for (i = 0; i < n; i++) |
|
printf(" ctr%d = %16llu [%s]\n", i, st->pctr_hwc[i], |
|
pctr_fn2str(st->pctr_fn[i])); |
|
if (tsc_avail) |
|
printf(" tsc = %16llu\n", st->pctr_tsc); |
|
printf(" idl = %16llu\n", st->pctr_idl); |
|
break; |
|
} |
|
} |
|
|
|
static int |
|
pctr_read(struct pctrst *st) |
|
{ |
|
int fd, se; |
|
|
|
fd = open(_PATH_PCTR, O_RDONLY); |
|
if (fd < 0) |
|
return (-1); |
|
if (ioctl(fd, PCIOCRD, st) < 0) { |
|
se = errno; |
|
close(fd); |
|
errno = se; |
|
return (-1); |
|
} |
|
return (close(fd)); |
|
} |
|
|
|
static int |
|
pctr_write(int ctr, u_int32_t val) |
|
{ |
|
int fd, se; |
|
|
|
fd = open(_PATH_PCTR, O_WRONLY); |
|
if (fd < 0) |
|
return (-1); |
|
if (ioctl(fd, PCIOCS0 + ctr, &val) < 0) { |
|
se = errno; |
|
close(fd); |
|
errno = se; |
|
return (-1); |
|
} |
|
return (close(fd)); |
|
} |
|
|
|
static __inline void |
|
pctr_printdesc(char *desc) |
|
{ |
char *p; |
char *p; |
|
|
for (;;) { |
for (;;) { |
|
|
while (*--p == ' ') |
while (*--p == ' ') |
; |
; |
p++; |
p++; |
printf(" %.*s\n", p - desc, desc); |
printf(" %.*s\n", (int)(p-desc), desc); |
desc = p; |
desc = p; |
} |
} |
} |
} |
|
|
/* Print all possible counter functions */ |
|
static void |
static void |
list(int fam) |
pctr_list_fnct(void) |
{ |
{ |
struct ctrfn *cfnp; |
struct ctrfn *cfnp = NULL; |
|
|
if (fam == 5) |
if (cpu_type == CPU_P5) |
cfnp = p5fn; |
cfnp = p5fn; |
else if (fam == 6) |
else if (cpu_type == CPU_P6) |
cfnp = p6fn; |
cfnp = p6fn; |
else { |
else if (cpu_type == CPU_CORE) |
fprintf(stderr, "Unknown CPU family %d\n", fam); |
cfnp = corefn; |
exit(1); |
else if (cpu_type == CPU_AMD) |
} |
cfnp = amdfn; |
printf("Hardware counter functions for the %s:\n\n", |
else |
fam == 5 ? "Pentium" : "Pentium Pro"); |
return; |
|
|
for (; cfnp->name; cfnp++) { |
for (; cfnp->name; cfnp++) { |
printf("%02x %s", cfnp->fn, cfnp->name); |
printf("%02x %s", cfnp->fn, cfnp->name); |
if (cfnp->flags & CFL_MESI) |
if (cfnp->flags & CFL_MESI) |
printf("/mesi"); |
printf(" (MESI)"); |
else if (cfnp->flags & CFL_SA) |
else if (cfnp->flags & CFL_SA) |
printf("/a"); |
printf(" (A)"); |
if (cfnp->flags & CFL_C0) |
if (cfnp->flags & CFL_C0) |
printf(" (ctr0 only)"); |
printf(" (ctr0 only)"); |
if (cfnp->flags & CFL_C1) |
else if (cfnp->flags & CFL_C1) |
printf(" (ctr1 only)"); |
printf(" (ctr1 only)"); |
printf("\n"); |
printf("\n"); |
if (cfnp->desc) |
if (cfnp->desc) |
printdesc(cfnp->desc); |
pctr_printdesc(cfnp->desc); |
} |
} |
} |
} |
|
|
static struct ctrfn * |
static int |
fn2cfnp(u_int family, u_int sel) |
pctr_set_cntr(void) |
{ |
{ |
struct ctrfn *cfnp; |
struct ctrfn *cfnp = NULL; |
|
u_int32_t val = func; |
|
int ind = 0; |
|
|
if (family == 6) { |
switch (cpu_type) { |
|
case CPU_P5: |
|
if (ctr >= PCTR_INTEL_NUM) |
|
return (EX_DATAERR); |
|
if (cflag) |
|
val |= PCTR_P5_C; |
|
if (kflag) |
|
val |= PCTR_P5_K; |
|
if (uflag) |
|
val |= PCTR_P5_U; |
|
if (func && (!kflag && !uflag)) |
|
val |= PCTR_P5_K | PCTR_P5_U; |
|
break; |
|
case CPU_P6: |
cfnp = p6fn; |
cfnp = p6fn; |
sel &= 0xff; |
case CPU_CORE: |
} else { |
cfnp = corefn; |
cfnp = p5fn; |
if (ctr >= PCTR_INTEL_NUM) |
sel &= 0x3f; |
return (EX_DATAERR); |
|
if (func && (ind = pctr_ctrfn_index(cfnp, func)) < 0) |
|
return (EX_DATAERR); |
|
if (func && cfnp[ind].flags & CFL_SA) |
|
val |= PCTR_X86_UM_A; |
|
if (Mflag && cfnp[ind].flags & CFL_MESI) |
|
val |= PCTR_X86_UM_M; |
|
if (Eflag && cfnp[ind].flags & CFL_MESI) |
|
val |= PCTR_X86_UM_E; |
|
if (Sflag && cfnp[ind].flags & CFL_MESI) |
|
val |= PCTR_X86_UM_S; |
|
if (Iflag && cfnp[ind].flags & CFL_MESI) |
|
val |= PCTR_X86_UM_I; |
|
if (func && (cfnp[ind].flags & CFL_MESI) && |
|
(!Mflag || !Eflag || !Sflag || !Iflag)) |
|
val |= PCTR_X86_UM_MESI; |
|
if (func && (cfnp[ind].flags & CFL_ED)) |
|
val |= PCTR_X86_E; |
|
case CPU_AMD: |
|
if (cpu_type == CPU_AMD && func && |
|
((ind = pctr_ctrfn_index(amdfn, func)) < 0)) |
|
return (EX_DATAERR); |
|
if (ctr >= PCTR_AMD_NUM) |
|
return (EX_DATAERR); |
|
if (eflag) |
|
val |= PCTR_X86_E; |
|
if (iflag) |
|
val |= PCTR_X86_I; |
|
if (kflag) |
|
val |= PCTR_X86_K; |
|
if (uflag) |
|
val |= PCTR_X86_U; |
|
if (func && (!kflag && !uflag)) |
|
val |= PCTR_X86_K | PCTR_X86_U; |
|
val |= masku << PCTR_X86_UM_SHIFT; |
|
val |= thold << PCTR_X86_CM_SHIFT; |
|
if (func) |
|
val |= PCTR_X86_EN; |
|
break; |
|
default: |
|
return (EX_UNAVAILABLE); |
} |
} |
for (; cfnp->name; cfnp++) |
|
if (cfnp->fn == sel) |
|
return (cfnp); |
|
return (NULL); |
|
} |
|
|
|
static char * |
return (pctr_write(ctr, val)); |
fn2str(int family, u_int sel) |
|
{ |
|
static char buf[128]; |
|
char um[9] = ""; |
|
char cm[6] = ""; |
|
struct ctrfn *cfnp; |
|
u_int fn; |
|
|
|
if (family == 5) { |
|
fn = sel & 0x3f; |
|
cfnp = fn2cfnp(family, fn); |
|
snprintf(buf, sizeof buf, "%c%c%c %02x %s", |
|
sel & P5CTR_C ? 'c' : '-', |
|
sel & P5CTR_U ? 'u' : '-', |
|
sel & P5CTR_K ? 'k' : '-', |
|
fn, cfnp ? cfnp->name : "unknown function"); |
|
} else if (family == 6) { |
|
fn = sel & 0xff; |
|
cfnp = fn2cfnp(family, fn); |
|
if (cfnp && cfnp->flags & CFL_MESI) |
|
snprintf(um, sizeof um, "/%c%c%c%c", |
|
sel & P6CTR_UM_M ? 'm' : '-', |
|
sel & P6CTR_UM_E ? 'e' : '-', |
|
sel & P6CTR_UM_S ? 's' : '-', |
|
sel & P6CTR_UM_I ? 'i' : '-'); |
|
else if (cfnp && cfnp->flags & CFL_SA) |
|
snprintf(um, sizeof um, "/%c", |
|
sel & P6CTR_UM_A ? 'a' : '-'); |
|
if (sel >> 24) |
|
snprintf(cm, sizeof cm, "+%d", sel >> 24); |
|
snprintf(buf, sizeof buf, "%c%c%c%c %02x%s%s%*s %s", |
|
sel & P6CTR_I ? 'i' : '-', |
|
sel & P6CTR_E ? 'e' : '-', |
|
sel & P6CTR_K ? 'k' : '-', |
|
sel & P6CTR_U ? 'u' : '-', |
|
fn, cm, um, 7 - (strlen(cm) + strlen(um)), "", |
|
cfnp ? cfnp->name : "unknown function"); |
|
} else |
|
return (NULL); |
|
return (buf); |
|
} |
} |
|
|
/* Print status of counters */ |
|
static void |
static void |
readst(void) |
usage(void) |
{ |
{ |
int fd, i; |
extern char *__progname; |
struct pctrst st; |
char *usg = NULL; |
|
|
fd = open(_PATH_PCTR, O_RDONLY); |
switch (cpu_type) { |
if (fd < 0) |
case CPU_P5: |
err(1, _PATH_PCTR); |
usg = "[-l] [-s ctr] [-cuk] [-f funct]"; |
if (ioctl(fd, PCIOCRD, &st) < 0) |
break; |
err(1, "PCIOCRD"); |
case CPU_P6: |
close(fd); |
case CPU_CORE: |
|
usg = "[-l] [-s ctr] [-eikuMESIA] [-f funct] [-m umask] " |
if (usep5ctr || usep6ctr) { |
"[-t thold]"; |
for (i = 0; i < PCTR_NUM; i++) |
break; |
printf(" ctr%d = %16qd [%s]\n", i, st.pctr_hwc[i], |
case CPU_AMD: |
fn2str(cpufamily, st.pctr_fn[i])); |
usg = "[-l] [-s ctr] [-eiku] [-f funct] [-m umask] " |
|
"[-t thold]"; |
|
break; |
} |
} |
printf(" tsc = %16qd\n idl = %16qd\n", st.pctr_tsc, st.pctr_idl); |
|
} |
|
|
|
static void |
fprintf(stderr, "%s: %s\n", __progname, usg); |
setctr(int ctr, u_int val) |
exit(EX_USAGE); |
{ |
|
int fd; |
|
|
|
fd = open(_PATH_PCTR, O_WRONLY); |
|
if (fd < 0) |
|
err(1, _PATH_PCTR); |
|
if (ioctl(fd, PCIOCS0 + ctr, &val) < 0) |
|
err(1, "PCIOCSn"); |
|
close(fd); |
|
} |
|
|
|
static void |
|
usage(void) |
|
{ |
|
fprintf(stderr, |
|
"usage:\n" |
|
" %s\n" |
|
" Read the counters.\n" |
|
" %s -l [5|6]\n" |
|
" List all possible counter functions for P5/P6.\n", |
|
__progname, __progname); |
|
if (usep5ctr) |
|
fprintf(stderr, |
|
" %s -s {0|1} [-[c][u][k]] function\n" |
|
" Configure counter.\n" |
|
" 0/1 - counter to configure\n" |
|
" c - count cycles not events\n" |
|
" u - count events in user mode (ring 3)\n" |
|
" k - count events in kernel mode (rings 0-2)\n", |
|
__progname); |
|
else if (usep6ctr) |
|
fprintf(stderr, |
|
" %s -s {0|1} [-[i][e][k][u]] " |
|
"function[+cm][/{[m][e][s][i]|[a]}]\n" |
|
" Configure counter.\n" |
|
" 0/1 - counter number to configure\n" |
|
" i - invert cm\n" |
|
" e - edge detect\n" |
|
" k - count events in kernel mode (rings 0-2)\n" |
|
" u - count events in user mode (ring 3)\n" |
|
" cm - # events/cycle required to bump ctr\n" |
|
" mesi - Modified/Exclusive/Shared/Invalid in cache\n" |
|
" s/a - self generated/all events\n", __progname); |
|
exit(1); |
|
} |
|
|
|
int |
|
main(int argc, char **argv) |
|
{ |
|
char *cp, **ap; |
|
u_int ctr, fn, fl = 0; |
|
struct ctrfn *cfnp; |
|
int mib[2], ac; |
|
size_t len; |
|
|
|
/* Get the kernel cpuid return values. */ |
|
mib[0] = CTL_MACHDEP; |
|
mib[1] = CPU_CPUVENDOR; |
|
if (sysctl(mib, 2, NULL, &len, NULL, 0) == -1) |
|
err(1, "sysctl CPU_CPUVENDOR"); |
|
if (len > sizeof(cpu_vendor)) /* Shouldn't ever happen. */ |
|
err(1, "sysctl CPU_CPUVENDOR too big"); |
|
if (sysctl(mib, 2, cpu_vendor, &len, NULL, 0) == -1) |
|
err(1, "sysctl CPU_CPUVENDOR"); |
|
|
|
mib[1] = CPU_CPUID; |
|
len = sizeof(cpu_id); |
|
if (sysctl(mib, 2, &cpu_id, &len, NULL, 0) == -1) |
|
err(1, "sysctl CPU_CPUID"); |
|
|
|
mib[1] = CPU_CPUFEATURE; |
|
len = sizeof(cpu_feature); |
|
if (sysctl(mib, 2, &cpu_feature, &len, NULL, 0) == -1) |
|
err(1, "sysctl CPU_CPUFEATURE"); |
|
|
|
pctr_isintel = (strcmp(cpu_vendor, "GenuineIntel") == 0); |
|
|
|
if (argc <= 1) |
|
readst(); |
|
else if (argc == 2 && !strcmp(argv[1], "-l")) |
|
list(cpufamily); |
|
else if (argc == 3 && !strcmp(argv[1], "-l")) |
|
list(atoi(argv[2])); |
|
else if (!strcmp(argv[1], "-s") && argc >= 4) { |
|
ctr = atoi(argv[2]); |
|
if (ctr >= PCTR_NUM) |
|
usage(); |
|
ap = &argv[3]; |
|
ac = argc - 3; |
|
|
|
if (usep6ctr) |
|
fl |= P6CTR_EN; |
|
if (**ap == '-') { |
|
cp = *ap; |
|
if (usep6ctr) { |
|
while (*++cp) |
|
switch (*cp) { |
|
case 'i': |
|
fl |= P6CTR_I; |
|
break; |
|
case 'e': |
|
fl |= P6CTR_E; |
|
break; |
|
case 'k': |
|
fl |= P6CTR_K; |
|
break; |
|
case 'u': |
|
fl |= P6CTR_U; |
|
break; |
|
default: |
|
usage(); |
|
} |
|
} else if (usep5ctr) { |
|
while (*++cp) |
|
switch (*cp) { |
|
case 'c': |
|
fl |= P5CTR_C; |
|
break; |
|
case 'k': |
|
fl |= P5CTR_K; |
|
break; |
|
case 'u': |
|
fl |= P5CTR_U; |
|
break; |
|
default: |
|
usage(); |
|
} |
|
} |
|
ap++; |
|
ac--; |
|
} else { |
|
if (usep6ctr) |
|
fl |= P6CTR_U|P6CTR_K; |
|
else if (usep5ctr) |
|
fl |= P5CTR_U|P5CTR_K; |
|
} |
|
|
|
if (!ac) |
|
usage(); |
|
|
|
fn = strtoul(*ap, NULL, 16); |
|
if ((usep6ctr && (fn & ~0xff)) || (!usep6ctr && (fn & ~0x3f))) |
|
usage(); |
|
fl |= fn; |
|
if (usep6ctr && (cp = strchr(*ap, '+'))) { |
|
cp++; |
|
fn = strtol(cp, NULL, 0); |
|
if (fn & ~0xff) |
|
usage(); |
|
fl |= (fn << 24); |
|
} |
|
cfnp = fn2cfnp(6, fl); |
|
if (usep6ctr && cfnp && (cp = strchr(*ap, '/'))) { |
|
if (cfnp->flags & CFL_MESI) { |
|
while (*++cp) |
|
switch (*cp) { |
|
case 'm': |
|
fl |= P6CTR_UM_M; |
|
break; |
|
case 'e': |
|
fl |= P6CTR_UM_E; |
|
break; |
|
case 's': |
|
fl |= P6CTR_UM_S; |
|
break; |
|
case 'i': |
|
fl |= P6CTR_UM_I; |
|
break; |
|
default: |
|
usage(); |
|
} |
|
} else if (cfnp->flags & CFL_SA) { |
|
while (*++cp) |
|
switch (*cp) { |
|
case 'a': |
|
fl |= P6CTR_UM_A; |
|
break; |
|
default: |
|
usage(); |
|
} |
|
} else |
|
usage(); |
|
} else if (cfnp && (cfnp->flags & CFL_MESI)) |
|
fl |= P6CTR_UM_MESI; |
|
ap++; |
|
ac--; |
|
|
|
if (ac) |
|
usage(); |
|
|
|
if (usep6ctr && ! (fl & 0xff)) |
|
fl = 0; |
|
setctr(ctr, fl); |
|
} else |
|
usage(); |
|
|
|
return 0; |
|
} |
} |