Annotation of src/usr.bin/pctr/pctr.c, Revision 1.7
1.7 ! mickey 1: /* $OpenBSD: pctr.c,v 1.6 2001/07/18 17:17:39 pvalchev Exp $ */
1.1 dm 2:
3: /*
4: * Pentium performance counter control program for OpenBSD.
5: * Copyright 1996 David Mazieres <dm@lcs.mit.edu>.
6: *
7: * Modification and redistribution in source and binary forms is
8: * permitted provided that due credit is given to the author and the
1.5 pvalchev 9: * OpenBSD project by leaving this copyright notice intact.
1.1 dm 10: */
11:
12: #include <stdio.h>
13: #include <stdlib.h>
14: #include <string.h>
1.6 pvalchev 15: #include <unistd.h>
1.4 downsj 16: #include <sys/param.h>
1.1 dm 17: #include <sys/types.h>
18: #include <sys/stat.h>
1.4 downsj 19: #include <sys/sysctl.h>
1.1 dm 20: #include <sys/ioctl.h>
1.4 downsj 21: #include <err.h>
1.1 dm 22: #include <fcntl.h>
23: #include <machine/cpu.h>
24: #include <machine/pctr.h>
1.4 downsj 25: #include <machine/specialreg.h>
1.1 dm 26:
27: #define CFL_MESI 0x1 /* Unit mask accepts MESI encoding */
28: #define CFL_SA 0x2 /* Unit mask accepts Self/Any bit */
29: #define CFL_C0 0x4 /* Counter 0 only */
30: #define CFL_C1 0x8 /* Counter 1 only */
31:
1.4 downsj 32: /* Kernel cpuid values. */
33: int cpu_id, cpu_feature;
34: char cpu_vendor[16];
35:
36: int pctr_isintel;
37:
38: #define usetsc (cpu_feature & CPUID_TSC)
39: #define usep5ctr (pctr_isintel && (((cpu_id >> 8) & 15) == 5) && \
40: (((cpu_id >> 4) & 15) > 0))
41: #define usep6ctr (pctr_isintel && ((cpu_id >> 8) & 15) == 6)
42: #define cpufamily ((cpu_id >> 8) & 15)
43:
44: extern char *__progname;
45:
1.1 dm 46: struct ctrfn {
1.7 ! mickey 47: u_int fn;
! 48: int flags;
! 49: char *name;
! 50: char *desc;
1.1 dm 51: };
52:
53: struct ctrfn p5fn[] = {
1.7 ! mickey 54: {0x00, 0, "Data read", NULL},
! 55: {0x01, 0, "Data write", NULL},
! 56: {0x02, 0, "Data TLB miss", NULL},
! 57: {0x03, 0, "Data read miss", NULL},
! 58: {0x04, 0, "Data write miss", NULL},
! 59: {0x05, 0, "Write (hit) to M or E state lines", NULL},
! 60: {0x06, 0, "Data cache lines written back", NULL},
! 61: {0x07, 0, "Data cache snoops", NULL},
! 62: {0x08, 0, "Data cache snoop hits", NULL},
! 63: {0x09, 0, "Memory accesses in both pipes", NULL},
! 64: {0x0a, 0, "Bank conflicts", NULL},
! 65: {0x0b, 0, "Misaligned data memory references", NULL},
! 66: {0x0c, 0, "Code read", NULL},
! 67: {0x0d, 0, "Code TLB miss", NULL},
! 68: {0x0e, 0, "Code cache miss", NULL},
! 69: {0x0f, 0, "Any segment register load", NULL},
! 70: {0x12, 0, "Branches", NULL},
! 71: {0x13, 0, "BTB hits", NULL},
! 72: {0x14, 0, "Taken branch or BTB hit", NULL},
! 73: {0x15, 0, "Pipeline flushes", NULL},
! 74: {0x16, 0, "Instructions executed", NULL},
! 75: {0x17, 0, "Instructions executed in the V-pipe", NULL},
! 76: {0x18, 0, "Bus utilization (clocks)", NULL},
! 77: {0x19, 0, "Pipeline stalled by write backup", NULL},
! 78: {0x1a, 0, "Pipeline stalled by data memory read", NULL},
! 79: {0x1b, 0, "Pipeline stalled by write to E or M line", NULL},
! 80: {0x1c, 0, "Locked bus cycle", NULL},
! 81: {0x1d, 0, "I/O read or write cycle", NULL},
! 82: {0x1e, 0, "Noncacheable memory references", NULL},
! 83: {0x1f, 0, "AGI (Address Generation Interlock)", NULL},
! 84: {0x22, 0, "Floating-point operations", NULL},
! 85: {0x23, 0, "Breakpoint 0 match", NULL},
! 86: {0x24, 0, "Breakpoint 1 match", NULL},
! 87: {0x25, 0, "Breakpoint 2 match", NULL},
! 88: {0x26, 0, "Breakpoint 3 match", NULL},
! 89: {0x27, 0, "Hardware interupts", NULL},
! 90: {0x28, 0, "Data read or data write", NULL},
! 91: {0x29, 0, "Data read miss or data write miss", NULL},
! 92: {0x0, 0, NULL, NULL},
1.1 dm 93: };
94:
95: struct ctrfn p6fn[] = {
1.7 ! mickey 96: {0x03, 0, "LD_BLOCKS",
! 97: "Number of store buffer blocks."},
! 98: {0x04, 0, "SB_DRAINS",
! 99: "Number of store buffer drain cycles."},
! 100: {0x05, 0, "MISALIGN_MEM_REF",
! 101: "Number of misaligned data memory references."},
! 102: {0x06, 0, "SEGMENT_REG_LOADS",
! 103: "Number of segment register loads."},
! 104: {0x10, CFL_C0, "FP_COMP_OPS_EXE",
! 105: "Number of computational floating-point operations executed."},
! 106: {0x11, CFL_C1, "FP_ASSIST",
! 107: "Number of floating-point exception cases handled by microcode."},
! 108: {0x12, CFL_C1, "MUL",
! 109: "Number of multiplies."},
! 110: {0x13, CFL_C1, "DIV",
! 111: "Number of divides."},
! 112: {0x14, CFL_C0, "CYCLES_DIV_BUSY",
! 113: "Number of cycles during which the divider is busy."},
! 114: {0x21, 0, "L2_ADS",
! 115: "Number of L2 address strobes."},
! 116: {0x22, 0, "L2_DBUS_BUSY",
! 117: "Number of cycles durring which the data bus was busy."},
! 118: {0x23, 0, "L2_DBUS_BUSY_RD",
! 119: "Number of cycles during which the data bus was busy transferring "
! 120: "data from L2 to the processor."},
! 121: {0x24, 0, "L2_LINES_IN",
! 122: "Number of lines allocated in the L2."},
! 123: {0x25, 0, "L2_M_LINES_INM",
! 124: "Number of modified lines allocated in the L2."},
! 125: {0x26, 0, "L2_LINES_OUT",
! 126: "Number of lines removed from the L2 for any reason."},
! 127: {0x27, 0, "L2_M_LINES_OUTM",
! 128: "Number of modified lines removed from the L2 for any reason."},
! 129: {0x28, CFL_MESI, "L2_IFETCH",
! 130: "Number of L2 instruction fetches."},
! 131: {0x29, CFL_MESI, "L2_LD",
! 132: "Number of L2 data loads."},
! 133: {0x2a, CFL_MESI, "L2_ST",
! 134: "Number of L2 data stores."},
! 135: {0x2e, CFL_MESI, "L2_RQSTS",
! 136: "Number of L2 requests."},
! 137: {0x43, 0, "DATA_MEM_REFS",
! 138: "All memory references, both cacheable and non-cacheable."},
! 139: {0x45, 0, "DCU_LINES_IN",
! 140: "Total lines allocated in the DCU."},
! 141: {0x46, 0, "DCU_M_LINES_IN",
! 142: "Number of M state lines allocated in the DCU."},
! 143: {0x47, 0, "DCU_M_LINES_OUT",
! 144: "Number of M state lines evicted from the DCU. "
! 145: "This includes evictions via snoop HITM, intervention or replacement"},
! 146: {0x48, 0, "DCU_MISS_OUTSTANDING",
! 147: "Weighted number of cycles while a DCU miss is outstanding."},
! 148: {0x60, 0, "BUS_REQ_OUTSTANDING",
! 149: "Number of bus requests outstanding."},
! 150: {0x61, 0, "BUS_BNR_DRV",
! 151: "Number of bus clock cycles during which the processor is "
! 152: "driving the BNR pin."},
! 153: {0x62, CFL_SA, "BUS_DRDY_CLOCKS",
! 154: "Number of clocks during which DRDY is asserted."},
! 155: {0x63, CFL_SA, "BUS_LOCK_CLOCKS",
! 156: "Number of clocks during which LOCK is asserted."},
! 157: {0x64, 0, "BUS_DATA_RCV",
! 158: "Number of bus clock cycles during which the processor is "
! 159: "receiving data."},
! 160: {0x65, CFL_SA, "BUS_TRAN_BRD",
! 161: "Number of burst read transactions."},
! 162: {0x66, CFL_SA, "BUS_TRAN_RFO",
! 163: "Number of read for ownership transactions."},
! 164: {0x67, CFL_SA, "BUS_TRANS_WB",
! 165: "Number of write back transactions."},
! 166: {0x68, CFL_SA, "BUS_TRAN_IFETCH",
! 167: "Number of instruction fetch transactions."},
! 168: {0x69, CFL_SA, "BUS_TRAN_INVAL",
! 169: "Number of invalidate transactions."},
! 170: {0x6a, CFL_SA, "BUS_TRAN_PWR",
! 171: "Number of partial write transactions."},
! 172: {0x6b, CFL_SA, "BUS_TRANS_P",
! 173: "Number of partial transactions."},
! 174: {0x6c, CFL_SA, "BUS_TRANS_IO",
! 175: "Number of I/O transactions."},
! 176: {0x6d, CFL_SA, "BUS_TRAN_DEF",
! 177: "Number of deferred transactions."},
! 178: {0x6e, CFL_SA, "BUS_TRAN_BURST",
! 179: "Number of burst transactions."},
! 180: {0x6f, CFL_SA, "BUS_TRAN_MEM",
! 181: "Number of memory transactions."},
! 182: {0x70, CFL_SA, "BUS_TRAN_ANY",
! 183: "Number of all transactions."},
! 184: {0x79, 0, "CPU_CLK_UNHALTED",
! 185: "Number of cycles during which the processor is not halted."},
! 186: {0x7a, 0, "BUS_HIT_DRV",
! 187: "Number of bus clock cycles during which the processor is "
! 188: "driving the HIT pin."},
! 189: {0x7b, 0, "BUS_HITM_DRV",
! 190: "Number of bus clock cycles during which the processor is "
! 191: "driving the HITM pin."},
! 192: {0x7e, 0, "BUS_SNOOP_STALL",
! 193: "Number of clock cycles during which the bus is snoop stalled."},
! 194: {0x80, 0, "IFU_IFETCH",
! 195: "Number of instruction fetches, both cacheable and non-cacheable."},
! 196: {0x81, 0, "IFU_IFETCH_MISS",
! 197: "Number of instruction fetch misses."},
! 198: {0x85, 0, "ITLB_MISS",
! 199: "Number of ITLB misses."},
! 200: {0x86, 0, "IFU_MEM_STALL",
! 201: "Number of cycles that the instruction fetch pipe stage is stalled, "
! 202: "including cache mises, ITLB misses, ITLB faults, "
! 203: "and victim cache evictions"},
! 204: {0x87, 0, "ILD_STALL",
! 205: "Number of cycles that the instruction length decoder is stalled"},
! 206: {0xa2, 0, "RESOURCE_STALLS",
! 207: "Number of cycles during which there are resource-related stalls."},
! 208: {0xc0, 0, "INST_RETIRED",
! 209: "Number of instructions retired."},
! 210: {0xc1, CFL_C0, "FLOPS",
! 211: "Number of computational floating-point operations retired."},
! 212: {0xc2, 0, "UOPS_RETIRED",
! 213: "Number of UOPs retired."},
! 214: {0xc4, 0, "BR_INST_RETIRED",
! 215: "Number of branch instructions retired."},
! 216: {0xc5, 0, "BR_MISS_PRED_RETIRED",
! 217: "Number of mispredicted branches retired."},
! 218: {0xc6, 0, "CYCLES_INT_MASKED",
! 219: "Number of processor cycles for which interrupts are disabled."},
! 220: {0xc7, 0, "CYCLES_INT_PENDING_AND_MASKED",
! 221: "Number of processor cycles for which interrupts are disabled "
! 222: "and interrupts are pending."},
! 223: {0xc8, 0, "HW_INT_RX",
! 224: "Number of hardware interrupts received."},
! 225: {0xc9, 0, "BR_TAKEN_RETIRED",
! 226: "Number of taken branches retired."},
! 227: {0xca, 0, "BR_MISS_PRED_TAKEN_RET",
! 228: "Number of taken mispredictioned branches retired."},
! 229: {0xd0, 0, "INST_DECODER",
! 230: "Number of instructions decoded."},
! 231: {0xd2, 0, "PARTIAL_RAT_STALLS",
! 232: "Number of cycles or events for partial stalls."},
! 233: {0xe0, 0, "BR_INST_DECODED",
! 234: "Number of branch instructions decoded."},
! 235: {0xe2, 0, "BTB_MISSES",
! 236: "Number of branches that miss the BTB."},
! 237: {0xe4, 0, "BR_BOGUS",
! 238: "Number of bogus branches."},
! 239: {0xe6, 0, "BACLEARS",
! 240: "Number of times BACLEAR is asserted."},
! 241: {0x0, 0, NULL, NULL},
1.1 dm 242: };
1.3 downsj 243:
1.1 dm 244: static void
245: printdesc (char *desc)
246: {
1.7 ! mickey 247: char *p;
1.1 dm 248:
1.7 ! mickey 249: for (;;) {
! 250: while (*desc == ' ')
! 251: desc++;
! 252: if (strlen(desc) < 70) {
! 253: if (*desc)
! 254: printf(" %s\n", desc);
! 255: return;
! 256: }
! 257: p = desc + 72;
! 258: while (*--p != ' ')
! 259: ;
! 260: while (*--p == ' ')
! 261: ;
! 262: p++;
! 263: printf(" %.*s\n", p - desc, desc);
! 264: desc = p;
! 265: }
1.1 dm 266: }
267:
268: /* Print all possible counter functions */
269: static void
270: list (int fam)
271: {
1.7 ! mickey 272: struct ctrfn *cfnp;
1.1 dm 273:
1.7 ! mickey 274: if (fam == 5)
! 275: cfnp = p5fn;
! 276: else if (fam == 6)
! 277: cfnp = p6fn;
! 278: else {
! 279: fprintf(stderr, "Unknown CPU family %d\n", fam);
! 280: exit (1);
! 281: }
! 282: printf("Hardware counter functions for the %s:\n\n",
! 283: fam == 5 ? "Pentium" : "Pentium Pro");
! 284: for (; cfnp->name; cfnp++) {
! 285: printf("%02x %s", cfnp->fn, cfnp->name);
! 286: if (cfnp->flags & CFL_MESI)
! 287: printf("/mesi");
! 288: else if (cfnp->flags & CFL_SA)
! 289: printf("/a");
! 290: if (cfnp->flags & CFL_C0)
! 291: printf(" (ctr0 only)");
! 292: if (cfnp->flags & CFL_C1)
! 293: printf(" (ctr1 only)");
! 294: printf("\n");
! 295: if (cfnp->desc)
! 296: printdesc(cfnp->desc);
! 297: }
1.1 dm 298: }
299:
300: struct ctrfn *
301: fn2cfnp (u_int family, u_int sel)
302: {
1.7 ! mickey 303: struct ctrfn *cfnp;
1.1 dm 304:
1.7 ! mickey 305: if (family == 6) {
! 306: cfnp = p6fn;
! 307: sel &= 0xff;
! 308: } else {
! 309: cfnp = p5fn;
! 310: sel &= 0x3f;
! 311: }
! 312: for (; cfnp->name; cfnp++)
! 313: if (cfnp->fn == sel)
! 314: return (cfnp);
! 315: return (NULL);
1.1 dm 316: }
317:
318: static char *
319: fn2str (int family, u_int sel)
320: {
1.7 ! mickey 321: static char buf[128];
! 322: char um[9] = "";
! 323: char cm[6] = "";
! 324: struct ctrfn *cfnp;
! 325: u_int fn;
! 326:
! 327: if (family == 5) {
! 328: fn = sel & 0x3f;
! 329: cfnp = fn2cfnp (family, fn);
! 330: sprintf(buf, "%c%c%c %02x %s",
! 331: sel & P5CTR_C ? 'c' : '-',
! 332: sel & P5CTR_U ? 'u' : '-',
! 333: sel & P5CTR_K ? 'k' : '-',
! 334: fn, cfnp ? cfnp->name : "unknown function");
! 335: }
! 336: else if (family == 6) {
! 337: fn = sel & 0xff;
! 338: cfnp = fn2cfnp (family, fn);
! 339: if (cfnp && cfnp->flags & CFL_MESI)
! 340: sprintf(um, "/%c%c%c%c",
! 341: sel & P6CTR_UM_M ? 'm' : '-',
! 342: sel & P6CTR_UM_E ? 'e' : '-',
! 343: sel & P6CTR_UM_S ? 's' : '-',
! 344: sel & P6CTR_UM_I ? 'i' : '-');
! 345: else if (cfnp && cfnp->flags & CFL_SA)
! 346: sprintf(um, "/%c", sel & P6CTR_UM_A ? 'a' : '-');
! 347: if (sel >> 24)
! 348: sprintf(cm, "+%d", sel >> 24);
! 349: sprintf(buf, "%c%c%c%c %02x%s%s%*s %s",
! 350: sel & P6CTR_I ? 'i' : '-',
! 351: sel & P6CTR_E ? 'e' : '-',
! 352: sel & P6CTR_K ? 'k' : '-',
! 353: sel & P6CTR_U ? 'u' : '-',
! 354: fn, cm, um, 7 - (strlen (cm) + strlen (um)), "",
! 355: cfnp ? cfnp->name : "unknown function");
! 356: }
! 357: else
! 358: return (NULL);
! 359: return (buf);
1.1 dm 360: }
361:
362: /* Print status of counters */
363: static void
364: readst (void)
365: {
1.7 ! mickey 366: int fd, i;
! 367: struct pctrst st;
1.1 dm 368:
1.7 ! mickey 369: fd = open (_PATH_PCTR, O_RDONLY);
! 370: if (fd < 0)
! 371: err (1, _PATH_PCTR);
! 372: if (ioctl (fd, PCIOCRD, &st) < 0)
! 373: err (1, "PCIOCRD");
! 374: close (fd);
! 375:
! 376: if (usep5ctr || usep6ctr) {
! 377: for (i = 0; i < PCTR_NUM; i++)
! 378: printf(" ctr%d = %16qd [%s]\n", i, st.pctr_hwc[i],
! 379: fn2str (cpufamily, st.pctr_fn[i]));
! 380: }
! 381: printf(" tsc = %16qd\n idl = %16qd\n", st.pctr_tsc, st.pctr_idl);
1.1 dm 382: }
383:
384: static void
385: setctr (int ctr, u_int val)
386: {
1.7 ! mickey 387: int fd;
1.1 dm 388:
1.7 ! mickey 389: fd = open (_PATH_PCTR, O_WRONLY);
! 390: if (fd < 0)
! 391: err (1, _PATH_PCTR);
! 392: if (ioctl (fd, PCIOCS0 + ctr, &val) < 0)
! 393: err (1, "PCIOCSn");
! 394: close (fd);
1.1 dm 395: }
396:
397: static void
398: usage (void)
399: {
1.7 ! mickey 400: fprintf(stderr,
1.1 dm 401: "usage:\n"
402: " %s\n"
403: " Read the counters.\n"
404: " %s -l [5|6]\n"
405: " List all possible counter functions for P5/P6.\n",
1.4 downsj 406: __progname, __progname);
1.7 ! mickey 407: if (usep5ctr)
! 408: fprintf(stderr,
1.1 dm 409: " %s -s {0|1} [-[c][u][k]] function\n"
410: " Configure counter.\n"
411: " 0/1 - counter to configure\n"
412: " c - count cycles not events\n"
413: " u - count events in user mode (ring 3)\n"
414: " k - count events in kernel mode (rings 0-2)\n",
1.4 downsj 415: __progname);
1.7 ! mickey 416: else if (usep6ctr)
! 417: fprintf(stderr,
1.1 dm 418: " %s -s {0|1} [-[i][e][k][u]] "
419: "function[+cm][/{[m][e][s][i]|[a]}]\n"
420: " Configure counter.\n"
421: " 0/1 - counter number to configure\n"
422: " i - invert cm\n"
423: " e - edge detect\n"
424: " k - count events in kernel mode (rings 0-2)\n"
425: " u - count events in user mode (ring 3)\n"
426: " cm - # events/cycle required to bump ctr\n"
427: " mesi - Modified/Exclusive/Shared/Invalid in cache\n"
1.4 downsj 428: " s/a - self generated/all events\n", __progname);
1.7 ! mickey 429: exit (1);
1.1 dm 430: }
431:
432: int
433: main (int argc, char **argv)
434: {
1.7 ! mickey 435: u_int ctr;
! 436: char *cp;
! 437: u_int fn, fl = 0;
! 438: char **ap;
! 439: int ac;
! 440: struct ctrfn *cfnp;
! 441: int mib[2];
! 442: size_t len;
! 443:
! 444: /* Get the kernel cpuid return values. */
! 445: mib[0] = CTL_MACHDEP;
! 446: mib[1] = CPU_CPUVENDOR;
! 447: if (sysctl(mib, 2, NULL, &len, NULL, 0) == -1)
! 448: err(1, "sysctl CPU_CPUVENDOR");
! 449: if (len > sizeof(cpu_vendor)) /* Shouldn't ever happen. */
! 450: err(1, "sysctl CPU_CPUVENDOR too big");
! 451: if (sysctl(mib, 2, cpu_vendor, &len, NULL, 0) == -1)
! 452: err(1, "sysctl CPU_CPUVENDOR");
! 453:
! 454: mib[1] = CPU_CPUID;
! 455: len = sizeof(cpu_id);
! 456: if (sysctl(mib, 2, &cpu_id, &len, NULL, 0) == -1)
! 457: err(1, "sysctl CPU_CPUID");
! 458:
! 459: mib[1] = CPU_CPUFEATURE;
! 460: len = sizeof(cpu_feature);
! 461: if (sysctl(mib, 2, &cpu_feature, &len, NULL, 0) == -1)
! 462: err(1, "sysctl CPU_CPUFEATURE");
! 463:
! 464: pctr_isintel = (strcmp(cpu_vendor, "GenuineIntel") == 0);
! 465:
! 466: if (argc <= 1)
! 467: readst ();
! 468: else if (argc == 2 && !strcmp (argv[1], "-l"))
! 469: list (cpufamily);
! 470: else if (argc == 3 && !strcmp (argv[1], "-l"))
! 471: list (atoi (argv[2]));
! 472: else if (!strcmp (argv[1], "-s") && argc >= 4) {
! 473: ctr = atoi (argv[2]);
! 474: if (ctr >= PCTR_NUM)
! 475: usage ();
! 476: ap = &argv[3];
! 477: ac = argc - 3;
! 478:
! 479: if (usep6ctr)
! 480: fl |= P6CTR_EN;
! 481: if (**ap == '-') {
! 482: cp = *ap;
! 483: if (usep6ctr)
! 484: while (*++cp)
! 485: switch (*cp) {
! 486: case 'i':
! 487: fl |= P6CTR_I;
! 488: break;
! 489: case 'e':
! 490: fl |= P6CTR_E;
! 491: break;
! 492: case 'k':
! 493: fl |= P6CTR_K;
! 494: break;
! 495: case 'u':
! 496: fl |= P6CTR_U;
! 497: break;
! 498: default:
! 499: usage ();
! 500: }
! 501: else if(usep5ctr)
! 502: while (*++cp)
! 503: switch (*cp) {
! 504: case 'c':
! 505: fl |= P5CTR_C;
! 506: break;
! 507: case 'k':
! 508: fl |= P5CTR_K;
! 509: break;
! 510: case 'u':
! 511: fl |= P5CTR_U;
! 512: break;
! 513: default:
! 514: usage ();
! 515: }
! 516: ap++;
! 517: ac--;
! 518: }
! 519: else {
! 520: if (usep6ctr)
! 521: fl |= P6CTR_U|P6CTR_K;
! 522: else if (usep5ctr)
! 523: fl |= P5CTR_U|P5CTR_K;
! 524: }
! 525:
! 526: if (!ac)
! 527: usage ();
! 528:
! 529: fn = strtoul (*ap, NULL, 16);
! 530: if ((usep6ctr && (fn & ~0xff)) || (!usep6ctr && (fn & ~0x3f)))
! 531: usage ();
! 532: fl |= fn;
! 533: if (usep6ctr && (cp = strchr (*ap, '+'))) {
! 534: cp++;
! 535: fn = strtol (cp, NULL, 0);
! 536: if (fn & ~0xff)
! 537: usage ();
! 538: fl |= (fn << 24);
! 539: }
! 540: cfnp = fn2cfnp (6, fl);
! 541: if (usep6ctr && cfnp && (cp = strchr (*ap, '/'))) {
! 542: if (cfnp->flags & CFL_MESI)
! 543: while (*++cp)
! 544: switch (*cp) {
! 545: case 'm':
! 546: fl |= P6CTR_UM_M;
! 547: break;
! 548: case 'e':
! 549: fl |= P6CTR_UM_E;
! 550: break;
! 551: case 's':
! 552: fl |= P6CTR_UM_S;
! 553: break;
! 554: case 'i':
! 555: fl |= P6CTR_UM_I;
! 556: break;
! 557: default:
! 558: usage ();
! 559: }
! 560: else if (cfnp->flags & CFL_SA)
! 561: while (*++cp)
! 562: switch (*cp) {
! 563: case 'a':
! 564: fl |= P6CTR_UM_A;
! 565: break;
! 566: default:
! 567: usage ();
! 568: }
! 569: else
! 570: usage ();
! 571: }
! 572: else if (cfnp && (cfnp->flags & CFL_MESI))
! 573: fl |= P6CTR_UM_MESI;
! 574: ap++;
! 575: ac--;
! 576:
! 577: if (ac)
! 578: usage ();
! 579:
! 580: if (usep6ctr && ! (fl & 0xff))
! 581: fl = 0;
! 582: setctr (ctr, fl);
! 583: }
! 584: else
! 585: usage ();
1.1 dm 586:
1.7 ! mickey 587: return 0;
1.1 dm 588: }
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