===================================================================
RCS file: /cvsrepo/anoncvs/cvs/src/usr.bin/pctr/pctrvar.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -c -r1.2 -r1.3
*** src/usr.bin/pctr/pctrvar.h	2007/10/17 14:54:30	1.2
--- src/usr.bin/pctr/pctrvar.h	2007/11/16 15:03:31	1.3
***************
*** 1,4 ****
! /*	$OpenBSD: pctrvar.h,v 1.2 2007/10/17 14:54:30 deraadt Exp $	*/
  
  /*
   * Copyright (c) 2007 Mike Belopuhov, Aleksey Lomovtsev
--- 1,4 ----
! /*	$OpenBSD: pctrvar.h,v 1.3 2007/11/16 15:03:31 mikeb Exp $	*/
  
  /*
   * Copyright (c) 2007 Mike Belopuhov, Aleksey Lomovtsev
***************
*** 49,54 ****
--- 49,55 ----
  #define CFL_C0			0x04	/* Counter 0 only */
  #define CFL_C1			0x08	/* Counter 1 only */
  #define CFL_ED			0x10	/* Edge detect is needed */
+ #define CFL_UM			0x20	/* Unit mask is mandatory */
  
  /* Pentium defines */
  #ifndef P5CTR_K
***************
*** 264,280 ****
  struct ctrfn corefn[] = {
  	{ 0x03, 0, "LD_BLOCKS",
  	 "Number of store buffer blocks." },
! 	{ 0x04, 0, "SB_DRAINS",
  	 "Number of store buffer drain cycles." },
! 	{ 0x06, 0, "SEGMENT_REG_LOADS",
  	 "Number of segment register loads." },
! 	{ 0x07, 0, "SSE_PRE_EXEC",
! 	 "Streaming SIMD Extensions Prefetch NTA instructions executed" },
! 	{ 0x08, 0, "DTLB_MISSES",
  	 "Memory accesses missed the DTLB" },
! 	{ 0x09, 0, "MEMORY_DISAMBIGUATION",
  	 "Memory disambiguation reset cycles" },
! 	{ 0x0c, 0, "PAGE_WALKS",
  	 "Number of page-walks executed" },
  	{ 0x10, 0, "FP_COMP_OPS_EXE",
  	 "Floating point computational micro-ops executed" },
--- 265,283 ----
  struct ctrfn corefn[] = {
  	{ 0x03, 0, "LD_BLOCKS",
  	 "Number of store buffer blocks." },
! 	{ 0x04, 0, "SD_DRAIN",
  	 "Number of store buffer drain cycles." },
! 	{ 0x05, 0, "MISALIGN_MEM_REF",
! 	 "Number of misaligned data memory references." },
! 	{ 0x06, 0, "SEG_REG_LOADS",
  	 "Number of segment register loads." },
! 	{ 0x07, 0, "SSE_PREF_RET",
! 	 "SSE software prefetch instructions retired." },
! 	{ 0x08, CFL_UM, "DTLB_MISSES",
  	 "Memory accesses missed the DTLB" },
! 	{ 0x09, CFL_UM, "MEMORY_DISAMBIGUATION",
  	 "Memory disambiguation reset cycles" },
! 	{ 0x0c, CFL_UM, "PAGE_WALKS",
  	 "Number of page-walks executed" },
  	{ 0x10, 0, "FP_COMP_OPS_EXE",
  	 "Floating point computational micro-ops executed" },
***************
*** 288,307 ****
  	 "Number of cycles during which the divider is busy." },
  	{ 0x18, 0, "IDLE_DURING_DIV",
  	 "Cycles the divider is busy and all other execution units are idle." },
! 	{ 0x19, 0, "DELAYED_BYPASS",
  	 "Delayed bypass to FP operation." },
! 	{ 0x21, 0, "L2_ADS",
  	 "Number of L2 address strobes." },
! 	{ 0x23, 0, "L2_DBUS_BUSY_RD",
  	 "Number of cycles during which the data bus was busy transferring "
  	 "data from L2 to the core."},
! 	{ 0x24, 0, "L2_LINES_IN",
  	 "Number of lines allocated in the L2 (L2 cache misses.)" },
! 	{ 0x25, 0, "L2_M_LINES_INM",
  	 "Number of modified lines allocated in the L2." },
! 	{ 0x26, 0, "L2_LINES_OUT",
  	 "Number of lines removed from the L2 for any reason." },
! 	{ 0x27, 0, "L2_M_LINES_OUTM",
  	 "Number of modified lines removed from the L2 for any reason." },
  	{ 0x28, CFL_MESI, "L2_IFETCH",
  	 "Number of L2 instruction fetches." },
--- 291,312 ----
  	 "Number of cycles during which the divider is busy." },
  	{ 0x18, 0, "IDLE_DURING_DIV",
  	 "Cycles the divider is busy and all other execution units are idle." },
! 	{ 0x19, CFL_UM, "DELAYED_BYPASS",
  	 "Delayed bypass to FP operation." },
! 	{ 0x21, CFL_UM, "L2_ADS",
  	 "Number of L2 address strobes." },
! 	{ 0x22, CFL_UM, "DBUS_BUSY",
! 	 "Number of cycles during which the data bus was busy." },
! 	{ 0x23, CFL_UM, "DBUS_BUSY_RD",
  	 "Number of cycles during which the data bus was busy transferring "
  	 "data from L2 to the core."},
! 	{ 0x24, CFL_UM, "L2_LINES_IN",
  	 "Number of lines allocated in the L2 (L2 cache misses.)" },
! 	{ 0x25, CFL_UM, "L2_M_LINES_IN",
  	 "Number of modified lines allocated in the L2." },
! 	{ 0x26, CFL_UM, "L2_LINES_OUT",
  	 "Number of lines removed from the L2 for any reason." },
! 	{ 0x27, CFL_UM, "L2_M_LINES_OUT",
  	 "Number of modified lines removed from the L2 for any reason." },
  	{ 0x28, CFL_MESI, "L2_IFETCH",
  	 "Number of L2 instruction fetches." },
***************
*** 317,394 ****
  	 "Number of cycles there is no request to access L2." },
  	{ 0x3a, 0, "EST_TRANS_ALL",
  	 "Number of any Intel Enhanced SpeedStep Technology transitions." },
! 	{ 0x3b, CFL_ED, "THERMAL_TRIP",
  	 "Duration in a thermal trip based on the current core clock." },
! 	{ 0x3c, 0, "NONHLT_REF_CYCLES",
! 	 "Number of non-halted bus cycles." },
! 	{ 0x40, CFL_MESI, "L1D_CACHE_LD",
  	 "L1 cacheable data reads." },
! 	{ 0x41, CFL_MESI, "L1D_CACHE_ST",
  	 "L1 cacheable data writes." },
! 	{ 0x42, CFL_MESI, "L1D_CACHE_LOCK",
  	 "L1 data cacheable locked reads." },
! 	{ 0x43, 0, "L1D_ALL_REF",
! 	 "All memory references to the L1 DCACHE."},
! 	{ 0x45, 0, "L1D_REPL",
  	 "Total lines allocated in the L1 DCACHE." },
! 	{ 0x46, 0, "L1D_M_REPL",
  	 "Number of M state lines allocated in the L1 DCACHE." },
! 	{ 0x47, 0, "L1D_M_EVICT",
! 	 "Number of M state lines evicted from the L1 DCACHE.  "
! 	 "This includes evictions via snoop HITM, intervention or "
! 	 "replacement." },
! 	{ 0x48, 0, "L1D_PEND_MISS",
  	 "Total number of outstanding L1 data cache misses at any cycle." },
! 	{ 0x49, 0, "DTLB_MISS",
  	 "Number of data references that missed TLB." },
  	{ 0x4b, 0, "SSE_PRE_MISS",
  	 "Number of cache misses by the SSE Prefetch NTA instructions." },
  	{ 0x4c, 0, "LOAD_HIT_PRE",
  	 "Load operations conflicting with a software prefetch." },
! 	{ 0x4e, 0, "L1D_PREFETCH",
  	 "L1 DCACHE prefetch requests" },
  	{ 0x4f, 0, "L1_PREF_REQ",
  	 "Number of L1 prefetch requests due to DCU cache misse.s" },
! 	{ 0x60, CFL_SA, "BUS_REQ_OUTSTANDING",
  	 "Number of bus requests outstanding." },
  	{ 0x61, CFL_SA, "BUS_BNR_DRV",
  	 "Number of bus clock cycles during which the processor is "
  	 "driving the BNR pin." },
  	{ 0x62, CFL_SA, "BUS_DRDY_CLOCKS",
  	 "Number of clocks during which DRDY is asserted." },
! 	{ 0x63, CFL_SA, "BUS_LOCK_CLOCKS",
  	 "Number of clocks during which LOCK is asserted." },
! 	{ 0x64, 0, "BUS_DATA_RCV",
  	 "Number of bus clock cycles during which the processor is "
  	 "receiving data." },
! 	{ 0x65, CFL_SA, "BUS_TRAN_BRD",
  	 "Number of burst read transactions." },
! 	{ 0x66, CFL_SA, "BUS_TRAN_RFO",
  	 "Number of read for ownership transactions." },
! 	{ 0x67, CFL_SA, "BUS_TRANS_WB",
  	 "Number of write back transactions." },
! 	{ 0x68, CFL_SA, "BUS_TRAN_IFETCH",
  	 "Number of instruction fetch transactions." },
! 	{ 0x69, CFL_SA, "BUS_TRAN_INVAL",
  	 "Number of invalidate transactions." },
! 	{ 0x6a, CFL_SA, "BUS_TRAN_PWR",
  	 "Number of partial write transactions." },
! 	{ 0x6b, CFL_SA, "BUS_TRANS_P",
  	 "Number of partial transactions." },
! 	{ 0x6c, CFL_SA, "BUS_TRANS_IO",
  	 "Number of I/O transactions." },
! 	{ 0x6d, CFL_SA, "BUS_TRAN_DEF",
  	 "Number of deferred transactions." },
! 	{ 0x6e, CFL_SA, "BUS_TRAN_BURST",
  	 "Number of burst transactions." },
! 	{ 0x6f, CFL_SA, "BUS_TRAN_MEM",
  	 "Number of memory transactions." },
! 	{ 0x70, CFL_SA, "BUS_TRAN_ANY",
  	 "Number of all transactions." },
  	{ 0x77, CFL_MESI, "BUS_SNOOPS",
  	 "Number of external bus cycles while bus lock signal asserted." },
! 	{ 0x78, 0, "CMP_SNOOP",
! 	 "Number of L1 DCACHE snoops by other core." },
  	{ 0x7a, CFL_SA, "BUS_HIT_DRV",
  	 "Number of bus clock cycles during which the processor is "
  	 "driving the HIT pin." },
--- 322,400 ----
  	 "Number of cycles there is no request to access L2." },
  	{ 0x3a, 0, "EST_TRANS_ALL",
  	 "Number of any Intel Enhanced SpeedStep Technology transitions." },
! 	{ 0x3b, CFL_ED|CFL_UM, "THERMAL_TRIP",
  	 "Duration in a thermal trip based on the current core clock." },
! 	{ 0x3c, CFL_UM, "CPU_CLK_UNHALTED",
! 	 "Number of non-halted cycles." },
! 	{ 0x40, CFL_MESI, "DCACHE_LD",
  	 "L1 cacheable data reads." },
! 	{ 0x41, CFL_MESI, "DCACHE_ST",
  	 "L1 cacheable data writes." },
! 	{ 0x42, CFL_MESI, "DCACHE_LOCK",
  	 "L1 data cacheable locked reads." },
! 	{ 0x43, CFL_UM, "DATA_MEM_REF",
! 	 "All memory references to the L1 DCACHE." },
! 	{ 0x44, CFL_UM, "DATA_MEM_CACHE_REF",
! 	 "All cacheable memory references to the L1 DCACHE." },
! 	{ 0x45, CFL_UM, "DCACHE_REPL",
  	 "Total lines allocated in the L1 DCACHE." },
! 	{ 0x46, 0, "DCACHE_M_REPL",
  	 "Number of M state lines allocated in the L1 DCACHE." },
! 	{ 0x47, 0, "DCACHE_M_EVICT",
! 	 "Number of M state lines evicted from the L1 DCACHE." },
! 	{ 0x48, 0, "DCACHE_PEND_MISS",
  	 "Total number of outstanding L1 data cache misses at any cycle." },
! 	{ 0x49, CFL_UM, "DTLB_MISS",
  	 "Number of data references that missed TLB." },
  	{ 0x4b, 0, "SSE_PRE_MISS",
  	 "Number of cache misses by the SSE Prefetch NTA instructions." },
  	{ 0x4c, 0, "LOAD_HIT_PRE",
  	 "Load operations conflicting with a software prefetch." },
! 	{ 0x4e, CFL_UM, "L1D_PREFETCH",
  	 "L1 DCACHE prefetch requests" },
  	{ 0x4f, 0, "L1_PREF_REQ",
  	 "Number of L1 prefetch requests due to DCU cache misse.s" },
! 	{ 0x60, CFL_SA|CFL_UM, "BUS_REQ_OUTSTANDING",
  	 "Number of bus requests outstanding." },
  	{ 0x61, CFL_SA, "BUS_BNR_DRV",
  	 "Number of bus clock cycles during which the processor is "
  	 "driving the BNR pin." },
  	{ 0x62, CFL_SA, "BUS_DRDY_CLOCKS",
  	 "Number of clocks during which DRDY is asserted." },
! 	{ 0x63, CFL_SA|CFL_UM, "BUS_LOCK_CLOCKS",
  	 "Number of clocks during which LOCK is asserted." },
! 	{ 0x64, CFL_UM, "BUS_DATA_RCV",
  	 "Number of bus clock cycles during which the processor is "
  	 "receiving data." },
! 	{ 0x65, CFL_SA|CFL_UM, "BUS_TRAN_BRD",
  	 "Number of burst read transactions." },
! 	{ 0x66, CFL_SA|CFL_UM, "BUS_TRAN_RFO",
  	 "Number of read for ownership transactions." },
! 	{ 0x67, CFL_SA|CFL_UM, "BUS_TRANS_WB",
  	 "Number of write back transactions." },
! 	{ 0x68, CFL_SA|CFL_UM, "BUS_TRAN_IFETCH",
  	 "Number of instruction fetch transactions." },
! 	{ 0x69, CFL_SA|CFL_UM, "BUS_TRAN_INVAL",
  	 "Number of invalidate transactions." },
! 	{ 0x6a, CFL_SA|CFL_UM, "BUS_TRAN_PWR",
  	 "Number of partial write transactions." },
! 	{ 0x6b, CFL_SA|CFL_UM, "BUS_TRANS_P",
  	 "Number of partial transactions." },
! 	{ 0x6c, CFL_SA|CFL_UM, "BUS_TRANS_IO",
  	 "Number of I/O transactions." },
! 	{ 0x6d, CFL_SA|CFL_UM, "BUS_TRAN_DEF",
  	 "Number of deferred transactions." },
! 	{ 0x6e, CFL_SA|CFL_UM, "BUS_TRAN_BURST",
  	 "Number of burst transactions." },
! 	{ 0x6f, CFL_SA|CFL_UM, "BUS_TRAN_MEM",
  	 "Number of memory transactions." },
! 	{ 0x70, CFL_SA|CFL_UM, "BUS_TRAN_ANY",
  	 "Number of all transactions." },
  	{ 0x77, CFL_MESI, "BUS_SNOOPS",
  	 "Number of external bus cycles while bus lock signal asserted." },
! 	{ 0x78, CFL_UM, "DCU_SNOOP_TO_SHARE",
! 	 "Number of DCU snoops to share-state L1 cache line due to "
! 	 "L1 misses." },
  	{ 0x7a, CFL_SA, "BUS_HIT_DRV",
  	 "Number of bus clock cycles during which the processor is "
  	 "driving the HIT pin." },
***************
*** 397,420 ****
  	 "driving the HITM pin." },
  	{ 0x7d, CFL_SA, "BUS_NOT_IN_USE",
  	 "Number of cycles there is no transaction from the core." },
! 	{ 0x7e, CFL_SA, "SNOOP_STALL_DRV",
  	 "Number of clock cycles during which the bus is snoop stalled." },
! 	{ 0x7f, 0, "BUS_IO_WAIT",
  	 "Number of cycles during which IO requests wait int the bus queue." },
! 	{ 0x80, 0, "L1I_READS",
  	 "Number of instruction fetches, both cacheable and non-cacheable." },
! 	{ 0x81, 0, "L1I_MISSES",
  	 "Number of instruction fetch misses." },
! 	{ 0x82, 0, "ITLB_MISS",
  	 "Number of ITLB misses." },
! 	{ 0x83, 0, "INSQ_QUEUE",
  	 "Cycles during which the instruction queue is full." },
! 	{ 0x85, 0, "ITLB_MISSES",
  	 "Number of ITLB misses." },
! 	{ 0x86, 0, "CYCLES_L1I_MEM_STALLED",
! 	 "Number of cycles that the instruction fetches stalled, "
! 	 "including cache mises, ITLB misses, ITLB faults, "
! 	 "and victim cache evictions" },
  	{ 0x87, 0, "ILD_STALL",
  	 "Number of cycles that the instruction length decoder is stalled." },
  	{ 0x88, 0, "BR_INST_EXEC",
--- 403,424 ----
  	 "driving the HITM pin." },
  	{ 0x7d, CFL_SA, "BUS_NOT_IN_USE",
  	 "Number of cycles there is no transaction from the core." },
! 	{ 0x7e, 0, "BUS_SNOOP_STALL",
  	 "Number of clock cycles during which the bus is snoop stalled." },
! 	{ 0x7f, CFL_UM, "BUS_IO_WAIT",
  	 "Number of cycles during which IO requests wait int the bus queue." },
! 	{ 0x80, 0, "ICACHE_READS",
  	 "Number of instruction fetches, both cacheable and non-cacheable." },
! 	{ 0x81, 0, "ICACHE_MISSES",
  	 "Number of instruction fetch misses." },
! 	{ 0x82, CFL_UM, "ITLB_MISS",
  	 "Number of ITLB misses." },
! 	{ 0x83, CFL_UM, "INSQ_QUEUE",
  	 "Cycles during which the instruction queue is full." },
! 	{ 0x85, CFL_UM, "ITLB_MISSES",
  	 "Number of ITLB misses." },
! 	{ 0x86, 0, "IFU_MEM_STALL",
! 	 "Number of cycles when the instruction fetches stalled." },
  	{ 0x87, 0, "ILD_STALL",
  	 "Number of cycles that the instruction length decoder is stalled." },
  	{ 0x88, 0, "BR_INST_EXEC",
***************
*** 453,514 ****
  	 "Number of times a taken branch predicted taken with bubble 2." },
  	{ 0xa0, 0, "RS_UOPS_DISPATCHED",
  	 "Number of microops dispatched for execution." },
  	{ 0xa2, 0, "RESOURCE_STALL",
  	 "Number of cycles while there us a resource related stall." },
! 	{ 0xaa, 0, "MACRO_INSTS",
  	 "Number of instructions decoded (but not necessarily executed "
  	 "or retired)." },
! 	{ 0xab, 0, "ESP",
  	 "ESP register operations." },
  	{ 0xb0, 0, "SIMD_UOPS_EXEC",
  	 "Number of SIMD micro-ops executed (excluding stores)." },
  	{ 0xb1, 0, "SIMD_SAT_UOP_EXEC",
  	 "Number of SIMD saturated arithmetic micro-ops executed." },
! 	{ 0xb3, 0, "SIMD_UOP_TYPE_EXEC",
! 	 "Number of SIMD packed multiply micro-ops executed." },
! 	{ 0xc0, 0, "INST_RETIRED",
  	 "Number of instructions retired." },
! 	{ 0xc1, 0, "X87_OPS_RETIRED",
  	 "Number of computational floating-point operations retired." },
! 	{ 0xc2, 0, "UOPS_RETIRED",
  	 "Number of UOPs retired." },
! 	{ 0xc3, 0, "MACHINE_NUKES",
! 	 "Number of times the pipeline is restarted due to either "
! 	 "multithreaded memory ordering conflicts or memory disambiguation "
! 	 "misprediction." },
! 	{ 0xc4, 0, "BR_INST_RETIRED",
  	 "Number of branch instructions retired." },
! 	{ 0xc5, 0, "BR_MISS_PRED_RETIRED",
  	 "Number of mispredicted branches retired." },
  	{ 0xc6, 0, "CYCLES_INT_MASKED",
! 	 "Number of processor cycles for which interrupts are disabled." },
! 	{ 0xc7, 0, "SIMD_INST_RETIRED",
! 	 "Number of SSE instructions retired." },
! 	{ 0xc8, 0, "HW_INT_RCV",
  	 "Number of hardware interrupts received." },
! 	{ 0xc9, 0, "ITLB_MISS_RETIRED",
! 	 "Number of retired instructions that missed the ITLB when they "
! 	 "were fetched."},
! 	{ 0xca, 0, "SIMD_COMP_INST_RETIRED",
! 	 "Number of computational SSE instructions retired." },
  	{ 0xcb, 0, "MEM_LOAD_RETIRED",
  	 "Number of retired load operations that missed the L1 DCACHE." },
! 	{ 0xcc, 0, "FP_MMX_TRANS_TO_MMX",
! 	 "Number of the first MMX instructions following a floating-point "
! 	 "instruction." },
! 	{ 0xcd, 0, "SIMD_ASSIST",
! 	 "Number of SIMD assists invoked." },
! 	{ 0xce, 0, "SIMD_INSTR_RETIRED",
! 	 "Number of SIMD instructions that retired." },
! 	{ 0xcf, 0, "SIMD_SAT_INSTR_RETIRED",
! 	 "Number of saturated arithmetic SIMD instructions that retired." },
  	{ 0xd0, 0, "INSTR_DECODED",
  	 "Number of instructions decoded." },
! 	{ 0xd2, 0, "RAT_STALLS",
  	 "Number of cycles or events for partial stalls." },
! 	{ 0xd4, 0, "SEG_RENAME_STALLS",
  	 "Number of stalls due to the lack of renaming resources." },
! 	{ 0xd5, 0, "SEG_REG_RENAMES",
  	 "Number of times the segment register is renamed." },
  	{ 0xd7, 0, "ESP_UOPS",
  	 "Number of ESP folding instruction decoded." },
--- 457,517 ----
  	 "Number of times a taken branch predicted taken with bubble 2." },
  	{ 0xa0, 0, "RS_UOPS_DISPATCHED",
  	 "Number of microops dispatched for execution." },
+ 	{ 0xa1, CFL_UM, "RS_UOPS_DISPATCHED",
+ 	 "Number of cycles for which micro-ops dispatched for execution." },
  	{ 0xa2, 0, "RESOURCE_STALL",
  	 "Number of cycles while there us a resource related stall." },
! 	{ 0xaa, CFL_UM, "MACRO_INSTS",
  	 "Number of instructions decoded (but not necessarily executed "
  	 "or retired)." },
! 	{ 0xab, CFL_UM, "ESP",
  	 "ESP register operations." },
  	{ 0xb0, 0, "SIMD_UOPS_EXEC",
  	 "Number of SIMD micro-ops executed (excluding stores)." },
  	{ 0xb1, 0, "SIMD_SAT_UOP_EXEC",
  	 "Number of SIMD saturated arithmetic micro-ops executed." },
! 	{ 0xb3, CFL_UM, "SIMD_INT",
! 	 "Number of SIMD integer instructions executed." },
! 	{ 0xc0, 0, "INST_RET",
  	 "Number of instructions retired." },
! 	{ 0xc1, 0, "FP_COMP_INSTR_RET",
  	 "Number of computational floating-point operations retired." },
! 	{ 0xc2, 0, "UOPS_RET",
  	 "Number of UOPs retired." },
! 	{ 0xc3, 0, "SMC_DETECTED",
! 	 "Number of times self-modifying code condition detected." },
! 	{ 0xc4, 0, "BR_INST_RET",
  	 "Number of branch instructions retired." },
! 	{ 0xc5, 0, "BR_MISPRED_RET",
  	 "Number of mispredicted branches retired." },
  	{ 0xc6, 0, "CYCLES_INT_MASKED",
! 	 "Number of cycles for which interrupts are disabled." },
! 	{ 0xc7, 0, "CYCLES_INT_PENDING_MASKED",
! 	 "Number of cycles for which interrupts are disabled "
! 	 "and interrupts are pending." },
! 	{ 0xc8, 0, "HW_INT_RX",
  	 "Number of hardware interrupts received." },
! 	{ 0xc9, 0, "BR_TAKEN_RET",
! 	 "Number of taken branch instructions retired."},
! 	{ 0xca, 0, "BR_MISPRED_TAKEN_RET",
! 	 "Number of taken andmispredicted branch instructions retired." },
  	{ 0xcb, 0, "MEM_LOAD_RETIRED",
  	 "Number of retired load operations that missed the L1 DCACHE." },
! 	{ 0xcc, 0, "MMX_FP_TRANS",
! 	 "Number of transitions between MMX and X87." },
! 	{ 0xcd, 0, "MMX_ASSIST",
! 	 "Number of EMMS executed." },
! 	{ 0xce, 0, "MMX_INSTR_RET",
! 	 "Number of MMX instructions retired." },
! 	{ 0xcf, 0, "MMX_SAT_INSTR_RET",
! 	 "Number of MMX saturated arithmetic instructions retired." },
  	{ 0xd0, 0, "INSTR_DECODED",
  	 "Number of instructions decoded." },
! 	{ 0xd2, CFL_UM, "RAT_STALLS",
  	 "Number of cycles or events for partial stalls." },
! 	{ 0xd4, CFL_UM, "SEG_RENAME_STALLS",
  	 "Number of stalls due to the lack of renaming resources." },
! 	{ 0xd5, CFL_UM, "SEG_REG_RENAMES",
  	 "Number of times the segment register is renamed." },
  	{ 0xd7, 0, "ESP_UOPS",
  	 "Number of ESP folding instruction decoded." },
***************
*** 520,526 ****
  	 "Number of all fused uops retired." },
  	{ 0xdb, 0, "UNFUSION",
  	 "Number of all unfusion events in the ROB." },
! 	{ 0xdc, 0, "RESOURCE_STALLS",
  	 "Number of cycles when the number of instructions in the pipeline "
  	 "waiting for retirement reaches the limit the processor can handle." },
  	{ 0xe0, 0, "BR_INST_DECODED",
--- 523,529 ----
  	 "Number of all fused uops retired." },
  	{ 0xdb, 0, "UNFUSION",
  	 "Number of all unfusion events in the ROB." },
! 	{ 0xdc, CFL_UM, "RESOURCE_STALLS",
  	 "Number of cycles when the number of instructions in the pipeline "
  	 "waiting for retirement reaches the limit the processor can handle." },
  	{ 0xe0, 0, "BR_INST_DECODED",