version 1.1, 2007/10/17 02:30:23 |
version 1.2, 2007/10/17 14:54:30 |
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#define CFL_ED 0x10 /* Edge detect is needed */ |
#define CFL_ED 0x10 /* Edge detect is needed */ |
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/* Pentium defines */ |
/* Pentium defines */ |
#define PCTR_P5_K 0x040 |
#ifndef P5CTR_K |
#define PCTR_P5_U 0x080 |
#define P5CTR_K 0x040 |
#define PCTR_P5_C 0x100 |
#endif |
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#ifndef P5CTR_U |
/* AMD & Intel shared defines */ |
#define P5CTR_U 0x080 |
#define PCTR_X86_U 0x010000 |
#endif |
#define PCTR_X86_K 0x020000 |
#ifndef P5CTR_C |
#define PCTR_X86_E 0x040000 |
#define P5CTR_C 0x100 |
#define PCTR_X86_EN 0x400000 |
#endif |
#define PCTR_X86_I 0x800000 |
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#define PCTR_X86_UM_M 0x0800 |
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#define PCTR_X86_UM_E 0x0400 |
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#define PCTR_X86_UM_S 0x0200 |
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#define PCTR_X86_UM_I 0x0100 |
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#define PCTR_X86_UM_MESI (PCTR_X86_UM_M | PCTR_X86_UM_E | \ |
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PCTR_X86_UM_S | PCTR_X86_UM_I) |
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#define PCTR_X86_UM_A 0x2000 |
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#define PCTR_X86_UM_SHIFT 8 |
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#define PCTR_X86_CM_SHIFT 24 |
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struct ctrfn { |
struct ctrfn { |
u_int32_t fn; |
u_int32_t fn; |