Annotation of src/usr.bin/pctr/pctrvar.h, Revision 1.1
1.1 ! deraadt 1: /* $OpenBSD$ */
! 2:
! 3: /*
! 4: * Copyright (c) 2007 Mike Belopuhov, Aleksey Lomovtsev
! 5: *
! 6: * Permission to use, copy, modify, and distribute this software for any
! 7: * purpose with or without fee is hereby granted, provided that the above
! 8: * copyright notice and this permission notice appear in all copies.
! 9: *
! 10: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
! 11: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
! 12: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
! 13: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
! 14: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
! 15: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
! 16: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
! 17: */
! 18:
! 19: /*
! 20: * Pentium performance counter control program for OpenBSD.
! 21: * Copyright 1996 David Mazieres <dm@lcs.mit.edu>.
! 22: *
! 23: * Modification and redistribution in source and binary forms is
! 24: * permitted provided that due credit is given to the author and the
! 25: * OpenBSD project by leaving this copyright notice intact.
! 26: */
! 27:
! 28: #ifndef _PCTRVAR_H_
! 29: #define _PCTRVAR_H_
! 30:
! 31: #define ARCH_UNDEF 0
! 32: #define ARCH_I386 1
! 33: #define ARCH_AMD64 2
! 34:
! 35: #define CPU_UNDEF 0
! 36: #define CPU_P5 1
! 37: #define CPU_P6 2
! 38: #define CPU_CORE 3
! 39: #define CPU_AMD 4
! 40:
! 41: #define PCTR_AMD_NUM 4
! 42: #define PCTR_INTEL_NUM 2 /* Intel supports only 2 counters */
! 43:
! 44: #define PCTR_MAX_FUNCT 0xff
! 45: #define PCTR_MAX_UMASK 0xff
! 46:
! 47: #define CFL_MESI 0x01 /* Unit mask accepts MESI encoding */
! 48: #define CFL_SA 0x02 /* Unit mask accepts Self/Any bit */
! 49: #define CFL_C0 0x04 /* Counter 0 only */
! 50: #define CFL_C1 0x08 /* Counter 1 only */
! 51: #define CFL_ED 0x10 /* Edge detect is needed */
! 52:
! 53: /* Pentium defines */
! 54: #define PCTR_P5_K 0x040
! 55: #define PCTR_P5_U 0x080
! 56: #define PCTR_P5_C 0x100
! 57:
! 58: /* AMD & Intel shared defines */
! 59: #define PCTR_X86_U 0x010000
! 60: #define PCTR_X86_K 0x020000
! 61: #define PCTR_X86_E 0x040000
! 62: #define PCTR_X86_EN 0x400000
! 63: #define PCTR_X86_I 0x800000
! 64: #define PCTR_X86_UM_M 0x0800
! 65: #define PCTR_X86_UM_E 0x0400
! 66: #define PCTR_X86_UM_S 0x0200
! 67: #define PCTR_X86_UM_I 0x0100
! 68: #define PCTR_X86_UM_MESI (PCTR_X86_UM_M | PCTR_X86_UM_E | \
! 69: PCTR_X86_UM_S | PCTR_X86_UM_I)
! 70: #define PCTR_X86_UM_A 0x2000
! 71:
! 72: #define PCTR_X86_UM_SHIFT 8
! 73: #define PCTR_X86_CM_SHIFT 24
! 74:
! 75:
! 76: struct ctrfn {
! 77: u_int32_t fn;
! 78: int flags;
! 79: char *name;
! 80: char *desc;
! 81: };
! 82:
! 83: struct ctrfn p5fn[] = {
! 84: { 0x00, 0, "Data read", NULL },
! 85: { 0x01, 0, "Data write", NULL },
! 86: { 0x02, 0, "Data TLB miss", NULL },
! 87: { 0x03, 0, "Data read miss", NULL },
! 88: { 0x04, 0, "Data write miss", NULL },
! 89: { 0x05, 0, "Write (hit) to M or E state lines", NULL },
! 90: { 0x06, 0, "Data cache lines written back", NULL },
! 91: { 0x07, 0, "Data cache snoops", NULL },
! 92: { 0x08, 0, "Data cache snoop hits", NULL },
! 93: { 0x09, 0, "Memory accesses in both pipes", NULL },
! 94: { 0x0a, 0, "Bank conflicts", NULL },
! 95: { 0x0b, 0, "Misaligned data memory references", NULL },
! 96: { 0x0c, 0, "Code read", NULL },
! 97: { 0x0d, 0, "Code TLB miss", NULL },
! 98: { 0x0e, 0, "Code cache miss", NULL },
! 99: { 0x0f, 0, "Any segment register load", NULL },
! 100: { 0x12, 0, "Branches", NULL },
! 101: { 0x13, 0, "BTB hits", NULL },
! 102: { 0x14, 0, "Taken branch or BTB hit", NULL },
! 103: { 0x15, 0, "Pipeline flushes", NULL },
! 104: { 0x16, 0, "Instructions executed", NULL },
! 105: { 0x17, 0, "Instructions executed in the V-pipe", NULL },
! 106: { 0x18, 0, "Bus utilization (clocks)", NULL },
! 107: { 0x19, 0, "Pipeline stalled by write backup", NULL },
! 108: { 0x1a, 0, "Pipeline stalled by data memory read", NULL },
! 109: { 0x1b, 0, "Pipeline stalled by write to E or M line", NULL },
! 110: { 0x1c, 0, "Locked bus cycle", NULL },
! 111: { 0x1d, 0, "I/O read or write cycle", NULL },
! 112: { 0x1e, 0, "Noncacheable memory references", NULL },
! 113: { 0x1f, 0, "AGI (Address Generation Interlock)", NULL },
! 114: { 0x22, 0, "Floating-point operations", NULL },
! 115: { 0x23, 0, "Breakpoint 0 match", NULL },
! 116: { 0x24, 0, "Breakpoint 1 match", NULL },
! 117: { 0x25, 0, "Breakpoint 2 match", NULL },
! 118: { 0x26, 0, "Breakpoint 3 match", NULL },
! 119: { 0x27, 0, "Hardware interrupts", NULL },
! 120: { 0x28, 0, "Data read or data write", NULL },
! 121: { 0x29, 0, "Data read miss or data write miss", NULL },
! 122: { 0x0, 0, NULL, NULL },
! 123: };
! 124:
! 125: struct ctrfn p6fn[] = {
! 126: { 0x03, 0, "LD_BLOCKS",
! 127: "Number of store buffer blocks." },
! 128: { 0x04, 0, "SB_DRAINS",
! 129: "Number of store buffer drain cycles." },
! 130: { 0x05, 0, "MISALIGN_MEM_REF",
! 131: "Number of misaligned data memory references." },
! 132: { 0x06, 0, "SEGMENT_REG_LOADS",
! 133: "Number of segment register loads." },
! 134: { 0x10, CFL_C0, "FP_COMP_OPS_EXE",
! 135: "Number of computational floating-point operations executed." },
! 136: { 0x11, CFL_C1, "FP_ASSIST",
! 137: "Number of floating-point exception cases handled by microcode." },
! 138: { 0x12, CFL_C1, "MUL",
! 139: "Number of multiplies." },
! 140: { 0x13, CFL_C1, "DIV",
! 141: "Number of divides." },
! 142: { 0x14, CFL_C0, "CYCLES_DIV_BUSY",
! 143: "Number of cycles during which the divider is busy." },
! 144: { 0x21, 0, "L2_ADS",
! 145: "Number of L2 address strobes." },
! 146: { 0x22, 0, "L2_DBUS_BUSY",
! 147: "Number of cycles durring which the data bus was busy." },
! 148: { 0x23, 0, "L2_DBUS_BUSY_RD",
! 149: "Number of cycles during which the data bus was busy transferring "
! 150: "data from L2 to the processor." },
! 151: { 0x24, 0, "L2_LINES_IN",
! 152: "Number of lines allocated in the L2." },
! 153: { 0x25, 0, "L2_M_LINES_INM",
! 154: "Number of modified lines allocated in the L2." },
! 155: { 0x26, 0, "L2_LINES_OUT",
! 156: "Number of lines removed from the L2 for any reason." },
! 157: { 0x27, 0, "L2_M_LINES_OUTM",
! 158: "Number of modified lines removed from the L2 for any reason." },
! 159: { 0x28, CFL_MESI, "L2_IFETCH",
! 160: "Number of L2 instruction fetches." },
! 161: { 0x29, CFL_MESI, "L2_LD",
! 162: "Number of L2 data loads." },
! 163: { 0x2a, CFL_MESI, "L2_ST",
! 164: "Number of L2 data stores." },
! 165: { 0x2e, CFL_MESI, "L2_RQSTS",
! 166: "Number of L2 requests." },
! 167: { 0x43, 0, "DATA_MEM_REF",
! 168: "Number of all memory references, both cacheable and non-cacheable." },
! 169: { 0x44, 0, "DATA_MEM_CACHE_REF",
! 170: "Number of L1 data cacheable read and write operations." },
! 171: { 0x45, 0, "DCU_LINES_IN",
! 172: "Total lines allocated in the DCU." },
! 173: { 0x46, 0, "DCU_M_LINES_IN",
! 174: "Number of M state lines allocated in the DCU." },
! 175: { 0x47, 0, "DCU_M_LINES_OUT",
! 176: "Number of M state lines evicted from the DCU. "
! 177: "This includes evictions via snoop HITM, intervention or replacement" },
! 178: { 0x48, 0, "DCU_MISS_OUTSTANDING",
! 179: "Weighted number of cycles while a DCU miss is outstanding." },
! 180: { 0x60, 0, "BUS_REQ_OUTSTANDING",
! 181: "Number of bus requests outstanding." },
! 182: { 0x61, 0, "BUS_BNR_DRV",
! 183: "Number of bus clock cycles during which the processor is "
! 184: "driving the BNR pin." },
! 185: { 0x62, CFL_SA, "BUS_DRDY_CLOCKS",
! 186: "Number of clocks during which DRDY is asserted." },
! 187: { 0x63, CFL_SA, "BUS_LOCK_CLOCKS",
! 188: "Number of clocks during which LOCK is asserted." },
! 189: { 0x64, 0, "BUS_DATA_RCV",
! 190: "Number of bus clock cycles during which the processor is "
! 191: "receiving data." },
! 192: { 0x65, CFL_SA, "BUS_TRAN_BRD",
! 193: "Number of burst read transactions." },
! 194: { 0x66, CFL_SA, "BUS_TRAN_RFO",
! 195: "Number of read for ownership transactions." },
! 196: { 0x67, CFL_SA, "BUS_TRANS_WB",
! 197: "Number of write back transactions." },
! 198: { 0x68, CFL_SA, "BUS_TRAN_IFETCH",
! 199: "Number of instruction fetch transactions." },
! 200: { 0x69, CFL_SA, "BUS_TRAN_INVAL",
! 201: "Number of invalidate transactions." },
! 202: { 0x6a, CFL_SA, "BUS_TRAN_PWR",
! 203: "Number of partial write transactions." },
! 204: { 0x6b, CFL_SA, "BUS_TRANS_P",
! 205: "Number of partial transactions." },
! 206: { 0x6c, CFL_SA, "BUS_TRANS_IO",
! 207: "Number of I/O transactions." },
! 208: { 0x6d, CFL_SA, "BUS_TRAN_DEF",
! 209: "Number of deferred transactions." },
! 210: { 0x6e, CFL_SA, "BUS_TRAN_BURST",
! 211: "Number of burst transactions." },
! 212: { 0x6f, CFL_SA, "BUS_TRAN_MEM",
! 213: "Number of memory transactions." },
! 214: { 0x70, CFL_SA, "BUS_TRAN_ANY",
! 215: "Number of all transactions." },
! 216: { 0x79, 0, "CPU_CLK_UNHALTED",
! 217: "Number of cycles during which the processor is not halted." },
! 218: { 0x7a, 0, "BUS_HIT_DRV",
! 219: "Number of bus clock cycles during which the processor is "
! 220: "driving the HIT pin." },
! 221: { 0x7b, 0, "BUS_HITM_DRV",
! 222: "Number of bus clock cycles during which the processor is "
! 223: "driving the HITM pin." },
! 224: { 0x7e, 0, "BUS_SNOOP_STALL",
! 225: "Number of clock cycles during which the bus is snoop stalled." },
! 226: { 0x80, 0, "IFU_IFETCH",
! 227: "Number of instruction fetches, both cacheable and non-cacheable." },
! 228: { 0x81, 0, "IFU_IFETCH_MISS",
! 229: "Number of instruction fetch misses." },
! 230: { 0x85, 0, "ITLB_MISS",
! 231: "Number of ITLB misses." },
! 232: { 0x86, 0, "IFU_MEM_STALL",
! 233: "Number of cycles that the instruction fetch pipe stage is stalled, "
! 234: "including cache mises, ITLB misses, ITLB faults, "
! 235: "and victim cache evictions" },
! 236: { 0x87, 0, "ILD_STALL",
! 237: "Number of cycles that the instruction length decoder is stalled" },
! 238: { 0xa2, 0, "RESOURCE_STALLS",
! 239: "Number of cycles during which there are resource-related stalls." },
! 240: { 0xc0, 0, "INST_RETIRED",
! 241: "Number of instructions retired." },
! 242: { 0xc1, CFL_C0, "FLOPS",
! 243: "Number of computational floating-point operations retired." },
! 244: { 0xc2, 0, "UOPS_RETIRED",
! 245: "Number of UOPs retired." },
! 246: { 0xc4, 0, "BR_INST_RETIRED",
! 247: "Number of branch instructions retired." },
! 248: { 0xc5, 0, "BR_MISS_PRED_RETIRED",
! 249: "Number of mispredicted branches retired." },
! 250: { 0xc6, 0, "CYCLES_INT_MASKED",
! 251: "Number of processor cycles for which interrupts are disabled." },
! 252: { 0xc7, 0, "CYCLES_INT_PENDING_AND_MASKED",
! 253: "Number of processor cycles for which interrupts are disabled "
! 254: "and interrupts are pending." },
! 255: { 0xc8, 0, "HW_INT_RX",
! 256: "Number of hardware interrupts received." },
! 257: { 0xc9, 0, "BR_TAKEN_RETIRED",
! 258: "Number of taken branches retired." },
! 259: { 0xca, 0, "BR_MISS_PRED_TAKEN_RET",
! 260: "Number of taken mispredictioned branches retired." },
! 261: { 0xd0, 0, "INST_DECODER",
! 262: "Number of instructions decoded." },
! 263: { 0xd2, 0, "PARTIAL_RAT_STALLS",
! 264: "Number of cycles or events for partial stalls." },
! 265: { 0xe0, 0, "BR_INST_DECODED",
! 266: "Number of branch instructions decoded." },
! 267: { 0xe2, 0, "BTB_MISSES",
! 268: "Number of branches that miss the BTB." },
! 269: { 0xe4, 0, "BR_BOGUS",
! 270: "Number of bogus branches." },
! 271: { 0xe6, 0, "BACLEARS",
! 272: "Number of times BACLEAR is asserted." },
! 273: { 0x0, 0, NULL, NULL}
! 274: };
! 275:
! 276: struct ctrfn corefn[] = {
! 277: { 0x03, 0, "LD_BLOCKS",
! 278: "Number of store buffer blocks." },
! 279: { 0x04, 0, "SB_DRAINS",
! 280: "Number of store buffer drain cycles." },
! 281: { 0x06, 0, "SEGMENT_REG_LOADS",
! 282: "Number of segment register loads." },
! 283: { 0x07, 0, "SSE_PRE_EXEC",
! 284: "Streaming SIMD Extensions Prefetch NTA instructions executed" },
! 285: { 0x08, 0, "DTLB_MISSES",
! 286: "Memory accesses missed the DTLB" },
! 287: { 0x09, 0, "MEMORY_DISAMBIGUATION",
! 288: "Memory disambiguation reset cycles" },
! 289: { 0x0c, 0, "PAGE_WALKS",
! 290: "Number of page-walks executed" },
! 291: { 0x10, 0, "FP_COMP_OPS_EXE",
! 292: "Floating point computational micro-ops executed" },
! 293: { 0x11, 0, "FP_ASSIST",
! 294: "Number of floating-point exception cases handled by microcode." },
! 295: { 0x12, 0, "MUL",
! 296: "Number of multiplies." },
! 297: { 0x13, 0, "DIV",
! 298: "Number of divides." },
! 299: { 0x14, 0, "CYCLES_DIV_BUSY",
! 300: "Number of cycles during which the divider is busy." },
! 301: { 0x18, 0, "IDLE_DURING_DIV",
! 302: "Cycles the divider is busy and all other execution units are idle." },
! 303: { 0x19, 0, "DELAYED_BYPASS",
! 304: "Delayed bypass to FP operation." },
! 305: { 0x21, 0, "L2_ADS",
! 306: "Number of L2 address strobes." },
! 307: { 0x23, 0, "L2_DBUS_BUSY_RD",
! 308: "Number of cycles during which the data bus was busy transferring "
! 309: "data from L2 to the core."},
! 310: { 0x24, 0, "L2_LINES_IN",
! 311: "Number of lines allocated in the L2 (L2 cache misses.)" },
! 312: { 0x25, 0, "L2_M_LINES_INM",
! 313: "Number of modified lines allocated in the L2." },
! 314: { 0x26, 0, "L2_LINES_OUT",
! 315: "Number of lines removed from the L2 for any reason." },
! 316: { 0x27, 0, "L2_M_LINES_OUTM",
! 317: "Number of modified lines removed from the L2 for any reason." },
! 318: { 0x28, CFL_MESI, "L2_IFETCH",
! 319: "Number of L2 instruction fetches." },
! 320: { 0x29, CFL_MESI, "L2_LD",
! 321: "Number of L2 data loads." },
! 322: { 0x2a, CFL_MESI, "L2_ST",
! 323: "Number of L2 data stores." },
! 324: { 0x2e, CFL_MESI, "L2_RQSTS",
! 325: "Number of L2 requests." },
! 326: { 0x30, CFL_MESI, "L2_REJECT_CYCLES",
! 327: "Number of cycles L2 is busy and rejecting new requests." },
! 328: { 0x32, CFL_MESI, "L2_NO_REQUEST_CYCLES",
! 329: "Number of cycles there is no request to access L2." },
! 330: { 0x3a, 0, "EST_TRANS_ALL",
! 331: "Number of any Intel Enhanced SpeedStep Technology transitions." },
! 332: { 0x3b, CFL_ED, "THERMAL_TRIP",
! 333: "Duration in a thermal trip based on the current core clock." },
! 334: { 0x3c, 0, "NONHLT_REF_CYCLES",
! 335: "Number of non-halted bus cycles." },
! 336: { 0x40, CFL_MESI, "L1D_CACHE_LD",
! 337: "L1 cacheable data reads." },
! 338: { 0x41, CFL_MESI, "L1D_CACHE_ST",
! 339: "L1 cacheable data writes." },
! 340: { 0x42, CFL_MESI, "L1D_CACHE_LOCK",
! 341: "L1 data cacheable locked reads." },
! 342: { 0x43, 0, "L1D_ALL_REF",
! 343: "All memory references to the L1 DCACHE."},
! 344: { 0x45, 0, "L1D_REPL",
! 345: "Total lines allocated in the L1 DCACHE." },
! 346: { 0x46, 0, "L1D_M_REPL",
! 347: "Number of M state lines allocated in the L1 DCACHE." },
! 348: { 0x47, 0, "L1D_M_EVICT",
! 349: "Number of M state lines evicted from the L1 DCACHE. "
! 350: "This includes evictions via snoop HITM, intervention or "
! 351: "replacement." },
! 352: { 0x48, 0, "L1D_PEND_MISS",
! 353: "Total number of outstanding L1 data cache misses at any cycle." },
! 354: { 0x49, 0, "DTLB_MISS",
! 355: "Number of data references that missed TLB." },
! 356: { 0x4b, 0, "SSE_PRE_MISS",
! 357: "Number of cache misses by the SSE Prefetch NTA instructions." },
! 358: { 0x4c, 0, "LOAD_HIT_PRE",
! 359: "Load operations conflicting with a software prefetch." },
! 360: { 0x4e, 0, "L1D_PREFETCH",
! 361: "L1 DCACHE prefetch requests" },
! 362: { 0x4f, 0, "L1_PREF_REQ",
! 363: "Number of L1 prefetch requests due to DCU cache misse.s" },
! 364: { 0x60, CFL_SA, "BUS_REQ_OUTSTANDING",
! 365: "Number of bus requests outstanding." },
! 366: { 0x61, CFL_SA, "BUS_BNR_DRV",
! 367: "Number of bus clock cycles during which the processor is "
! 368: "driving the BNR pin." },
! 369: { 0x62, CFL_SA, "BUS_DRDY_CLOCKS",
! 370: "Number of clocks during which DRDY is asserted." },
! 371: { 0x63, CFL_SA, "BUS_LOCK_CLOCKS",
! 372: "Number of clocks during which LOCK is asserted." },
! 373: { 0x64, 0, "BUS_DATA_RCV",
! 374: "Number of bus clock cycles during which the processor is "
! 375: "receiving data." },
! 376: { 0x65, CFL_SA, "BUS_TRAN_BRD",
! 377: "Number of burst read transactions." },
! 378: { 0x66, CFL_SA, "BUS_TRAN_RFO",
! 379: "Number of read for ownership transactions." },
! 380: { 0x67, CFL_SA, "BUS_TRANS_WB",
! 381: "Number of write back transactions." },
! 382: { 0x68, CFL_SA, "BUS_TRAN_IFETCH",
! 383: "Number of instruction fetch transactions." },
! 384: { 0x69, CFL_SA, "BUS_TRAN_INVAL",
! 385: "Number of invalidate transactions." },
! 386: { 0x6a, CFL_SA, "BUS_TRAN_PWR",
! 387: "Number of partial write transactions." },
! 388: { 0x6b, CFL_SA, "BUS_TRANS_P",
! 389: "Number of partial transactions." },
! 390: { 0x6c, CFL_SA, "BUS_TRANS_IO",
! 391: "Number of I/O transactions." },
! 392: { 0x6d, CFL_SA, "BUS_TRAN_DEF",
! 393: "Number of deferred transactions." },
! 394: { 0x6e, CFL_SA, "BUS_TRAN_BURST",
! 395: "Number of burst transactions." },
! 396: { 0x6f, CFL_SA, "BUS_TRAN_MEM",
! 397: "Number of memory transactions." },
! 398: { 0x70, CFL_SA, "BUS_TRAN_ANY",
! 399: "Number of all transactions." },
! 400: { 0x77, CFL_MESI, "BUS_SNOOPS",
! 401: "Number of external bus cycles while bus lock signal asserted." },
! 402: { 0x78, 0, "CMP_SNOOP",
! 403: "Number of L1 DCACHE snoops by other core." },
! 404: { 0x7a, CFL_SA, "BUS_HIT_DRV",
! 405: "Number of bus clock cycles during which the processor is "
! 406: "driving the HIT pin." },
! 407: { 0x7b, CFL_SA, "BUS_HITM_DRV",
! 408: "Number of bus clock cycles during which the processor is "
! 409: "driving the HITM pin." },
! 410: { 0x7d, CFL_SA, "BUS_NOT_IN_USE",
! 411: "Number of cycles there is no transaction from the core." },
! 412: { 0x7e, CFL_SA, "SNOOP_STALL_DRV",
! 413: "Number of clock cycles during which the bus is snoop stalled." },
! 414: { 0x7f, 0, "BUS_IO_WAIT",
! 415: "Number of cycles during which IO requests wait int the bus queue." },
! 416: { 0x80, 0, "L1I_READS",
! 417: "Number of instruction fetches, both cacheable and non-cacheable." },
! 418: { 0x81, 0, "L1I_MISSES",
! 419: "Number of instruction fetch misses." },
! 420: { 0x82, 0, "ITLB_MISS",
! 421: "Number of ITLB misses." },
! 422: { 0x83, 0, "INSQ_QUEUE",
! 423: "Cycles during which the instruction queue is full." },
! 424: { 0x85, 0, "ITLB_MISSES",
! 425: "Number of ITLB misses." },
! 426: { 0x86, 0, "CYCLES_L1I_MEM_STALLED",
! 427: "Number of cycles that the instruction fetches stalled, "
! 428: "including cache mises, ITLB misses, ITLB faults, "
! 429: "and victim cache evictions" },
! 430: { 0x87, 0, "ILD_STALL",
! 431: "Number of cycles that the instruction length decoder is stalled." },
! 432: { 0x88, 0, "BR_INST_EXEC",
! 433: "Number of branch instructions executed." },
! 434: { 0x89, 0, "BR_MISSP_EXEC",
! 435: "Number of mispredicted branch instructions that were executed." },
! 436: { 0x8a, 0, "BR_BAC_MISSP_EXEC",
! 437: "Number of branch instructions that were mispredicted at decoding." },
! 438: { 0x8b, 0, "BR_CND_EXEC",
! 439: "Number of conditional branch instructions executed, but not "
! 440: "necessarily retired." },
! 441: { 0x8c, 0, "BR_CND_MISSP_EXEC",
! 442: "Number of mispredicted conditional branch instructions that "
! 443: "were executed." },
! 444: { 0x8d, 0, "BR_IND_EXEC",
! 445: "Number of indirect branch instructions that were executed." },
! 446: { 0x8e, 0, "BR_IND_MISSP_EXEC",
! 447: "number of mispredicted indirect branch instructions that were "
! 448: "executed." },
! 449: { 0x8f, 0, "BR_RET_EXEC",
! 450: "Number of RET instructions that were executed." },
! 451: { 0x90, 0, "BR_RET_MISSP_EXEC",
! 452: "Number of mispredicted RET instructions that were executed." },
! 453: { 0x91, 0, "BR_RET_BAC_MISSP_EXEC",
! 454: "Number of RET instructions that were executed and were mispredicted "
! 455: "at decoding." },
! 456: { 0x92, 0, "BR_CALL_EXEC",
! 457: "Number of CALL instructions executed." },
! 458: { 0x93, 0, "BR_CALL_MISSP_EXEC",
! 459: "Number of mispredicted CALL instructions that were executed." },
! 460: { 0x94, 0, "BR_IND_CALL_EXEC",
! 461: "Number of indirect CALL instructions that were executed." },
! 462: { 0x97, 0, "BR_TKN_BUBBLE_1",
! 463: "Number of times a taken branch predicted taken with bubble 1." },
! 464: { 0x98, 0, "BR_TKN_BUBBLE_2",
! 465: "Number of times a taken branch predicted taken with bubble 2." },
! 466: { 0xa0, 0, "RS_UOPS_DISPATCHED",
! 467: "Number of microops dispatched for execution." },
! 468: { 0xa2, 0, "RESOURCE_STALL",
! 469: "Number of cycles while there us a resource related stall." },
! 470: { 0xaa, 0, "MACRO_INSTS",
! 471: "Number of instructions decoded (but not necessarily executed "
! 472: "or retired)." },
! 473: { 0xab, 0, "ESP",
! 474: "ESP register operations." },
! 475: { 0xb0, 0, "SIMD_UOPS_EXEC",
! 476: "Number of SIMD micro-ops executed (excluding stores)." },
! 477: { 0xb1, 0, "SIMD_SAT_UOP_EXEC",
! 478: "Number of SIMD saturated arithmetic micro-ops executed." },
! 479: { 0xb3, 0, "SIMD_UOP_TYPE_EXEC",
! 480: "Number of SIMD packed multiply micro-ops executed." },
! 481: { 0xc0, 0, "INST_RETIRED",
! 482: "Number of instructions retired." },
! 483: { 0xc1, 0, "X87_OPS_RETIRED",
! 484: "Number of computational floating-point operations retired." },
! 485: { 0xc2, 0, "UOPS_RETIRED",
! 486: "Number of UOPs retired." },
! 487: { 0xc3, 0, "MACHINE_NUKES",
! 488: "Number of times the pipeline is restarted due to either "
! 489: "multithreaded memory ordering conflicts or memory disambiguation "
! 490: "misprediction." },
! 491: { 0xc4, 0, "BR_INST_RETIRED",
! 492: "Number of branch instructions retired." },
! 493: { 0xc5, 0, "BR_MISS_PRED_RETIRED",
! 494: "Number of mispredicted branches retired." },
! 495: { 0xc6, 0, "CYCLES_INT_MASKED",
! 496: "Number of processor cycles for which interrupts are disabled." },
! 497: { 0xc7, 0, "SIMD_INST_RETIRED",
! 498: "Number of SSE instructions retired." },
! 499: { 0xc8, 0, "HW_INT_RCV",
! 500: "Number of hardware interrupts received." },
! 501: { 0xc9, 0, "ITLB_MISS_RETIRED",
! 502: "Number of retired instructions that missed the ITLB when they "
! 503: "were fetched."},
! 504: { 0xca, 0, "SIMD_COMP_INST_RETIRED",
! 505: "Number of computational SSE instructions retired." },
! 506: { 0xcb, 0, "MEM_LOAD_RETIRED",
! 507: "Number of retired load operations that missed the L1 DCACHE." },
! 508: { 0xcc, 0, "FP_MMX_TRANS_TO_MMX",
! 509: "Number of the first MMX instructions following a floating-point "
! 510: "instruction." },
! 511: { 0xcd, 0, "SIMD_ASSIST",
! 512: "Number of SIMD assists invoked." },
! 513: { 0xce, 0, "SIMD_INSTR_RETIRED",
! 514: "Number of SIMD instructions that retired." },
! 515: { 0xcf, 0, "SIMD_SAT_INSTR_RETIRED",
! 516: "Number of saturated arithmetic SIMD instructions that retired." },
! 517: { 0xd0, 0, "INSTR_DECODED",
! 518: "Number of instructions decoded." },
! 519: { 0xd2, 0, "RAT_STALLS",
! 520: "Number of cycles or events for partial stalls." },
! 521: { 0xd4, 0, "SEG_RENAME_STALLS",
! 522: "Number of stalls due to the lack of renaming resources." },
! 523: { 0xd5, 0, "SEG_REG_RENAMES",
! 524: "Number of times the segment register is renamed." },
! 525: { 0xd7, 0, "ESP_UOPS",
! 526: "Number of ESP folding instruction decoded." },
! 527: { 0xd8, 0, "SIMD_FD_RET",
! 528: "Number of SSE/SSE2 instructions retired." },
! 529: { 0xd9, 0, "SIMD_FP_COM_RET",
! 530: "Number of SSE/SSE2 compute instructions retired." },
! 531: { 0xda, 0, "FUSED_UOPS_RET",
! 532: "Number of all fused uops retired." },
! 533: { 0xdb, 0, "UNFUSION",
! 534: "Number of all unfusion events in the ROB." },
! 535: { 0xdc, 0, "RESOURCE_STALLS",
! 536: "Number of cycles when the number of instructions in the pipeline "
! 537: "waiting for retirement reaches the limit the processor can handle." },
! 538: { 0xe0, 0, "BR_INST_DECODED",
! 539: "Number of branch instructions decoded." },
! 540: { 0xe2, 0, "BTB_MISSES",
! 541: "Number of branches the BTB did not produce a prediction." },
! 542: { 0xe4, 0, "BOGUS_BR",
! 543: "Number of byte sequences that were mistakenly detected as taken "
! 544: "branch instructions." },
! 545: { 0xe6, 0, "BACLEARS",
! 546: "Number of times BACLEAR is asserted." },
! 547: { 0xf0, 0, "PREF_RQSTS_UP",
! 548: "Number of upward prefetches issued from the Data Prefetch Logic "
! 549: "(DPL) to the L2 cache." },
! 550: { 0xf8, 0, "PREF_RQSTS_DN",
! 551: "Number of downward prefetches issued from the Data Prefetch Logic "
! 552: "(DPL) to the L2 cache." },
! 553: { 0x0, 0, NULL, NULL }
! 554: };
! 555:
! 556: struct ctrfn amdfn[] = {
! 557: { 0x00, 0, "Dispatched FPU operations", NULL },
! 558: { 0x01, 0, "Cycles with no FPU ops retired", NULL },
! 559: { 0x02, 0, "Dispatched fast flag FPU operations", NULL },
! 560: { 0x20, 0, "Segment register loads", NULL },
! 561: { 0x21, 0, "Pipeline restart due to self-modifying code", NULL },
! 562: { 0x22, 0, "Pipeline restart due to probe hit", NULL },
! 563: { 0x23, 0, "LS2 buffer is full", NULL },
! 564: { 0x24, 0, "Locked operations", NULL },
! 565: { 0x26, 0, "Retired CFLUSH instructions", NULL },
! 566: { 0x27, 0, "Retired CPUID instructions", NULL },
! 567: { 0x40, 0, "Data cache accesses", NULL },
! 568: { 0x41, 0, "Data cache misses", NULL },
! 569: { 0x42, 0, "Data cache refills from L2 or system", NULL },
! 570: { 0x43, 0, "Data cache refills from system", NULL },
! 571: { 0x44, 0, "Data cache lines evicted", NULL },
! 572: { 0x45, 0, "L1 DTLB miss and L2 DTLB hit", NULL },
! 573: { 0x46, 0, "L1 DTLB miss and L2 DTLB miss", NULL },
! 574: { 0x47, 0, "Misaligned access", NULL },
! 575: { 0x48, 0, "Microarchitectural late cancel of an access", NULL },
! 576: { 0x49, 0, "Microarchitectural early cancel of an access", NULL },
! 577: { 0x4a, 0, "Single bit ECC errors recorded by scrubber", NULL },
! 578: { 0x4b, 0, "Prefetch instructions dispatched", NULL },
! 579: { 0x4c, 0, "DCACHE misses by locked instructions", NULL },
! 580: { 0x65, 0, "Memory requests by type", NULL },
! 581: { 0x67, 0, "Data prefetcher", NULL },
! 582: { 0x6c, 0, "System read responses by coherency state", NULL },
! 583: { 0x6d, 0, "Quadwords written to system", NULL },
! 584: { 0x76, 0, "CPU clocks not halted", NULL },
! 585: { 0x7d, 0, "Requests to L2 cache", NULL },
! 586: { 0x7e, 0, "L2 cache misses", NULL },
! 587: { 0x7f, 0, "L2 cache fill/writeback", NULL },
! 588: { 0x80, 0, "ICACHE fetches", NULL },
! 589: { 0x81, 0, "ICACHE misses", NULL },
! 590: { 0x82, 0, "ICACHE refills from L2", NULL },
! 591: { 0x83, 0, "ICACHE refills from system", NULL },
! 592: { 0x84, 0, "L1 ITLB miss and L2 ITLB hit", NULL },
! 593: { 0x85, 0, "L1 ITLB miss and L2 ITLB miss", NULL },
! 594: { 0x86, 0, "Pipeline restart due to instruction stream probe", NULL },
! 595: { 0x87, 0, "Instruction fetch stall", NULL },
! 596: { 0x88, 0, "Return stack hits", NULL },
! 597: { 0x89, 0, "Return stack overflows", NULL },
! 598: { 0xc0, 0, "Retired instructions", NULL },
! 599: { 0xc1, 0, "Retired microops", NULL },
! 600: { 0xc2, 0, "Retired branch instructions", NULL },
! 601: { 0xc3, 0, "Retired mispredicted branch instructions", NULL },
! 602: { 0xc4, 0, "Retired taken branch instructions", NULL },
! 603: { 0xc5, 0, "Retired mispredicted taken branch instructions", NULL },
! 604: { 0xc6, 0, "Retired far control transfers", NULL },
! 605: { 0xc7, 0, "Retired branch resyncs", NULL },
! 606: { 0xc8, 0, "Retired near returns", NULL },
! 607: { 0xc9, 0, "Retired mispredicted near returns", NULL },
! 608: { 0xca, 0, "Retired mispredicted indirect brnaches", NULL },
! 609: { 0xcb, 0, "Retired MMX/FP instructions", NULL },
! 610: { 0xcc, 0, "Retired fastpath double op instructions", NULL },
! 611: { 0xcd, 0, "Interrupts-masked cycles", NULL },
! 612: { 0xce, 0, "Interrupts-masked cycles with interrupts pending", NULL },
! 613: { 0xcf, 0, "Interrupts taken", NULL },
! 614: { 0xd0, 0, "Decoder empty", NULL },
! 615: { 0xd1, 0, "Dispatch stalls", NULL },
! 616: { 0xd2, 0, "Dispatch stalls for branch abort retire", NULL },
! 617: { 0xd3, 0, "Dispatch stalls for serialisation", NULL },
! 618: { 0xd4, 0, "Dispatch stalls for segment load", NULL },
! 619: { 0xd5, 0, "Dispatch stalls for reoder buffer full", NULL },
! 620: { 0xd6, 0, "Dispatch stalls for reservation station full", NULL },
! 621: { 0xd7, 0, "Dispatch stalls for FPU full", NULL },
! 622: { 0xd8, 0, "Dispatch stalls for LS full", NULL },
! 623: { 0xd9, 0, "Dispatch stalls waiting for all quite", NULL },
! 624: { 0xda, 0, "Dispatch stalls for far transfer or resync to retire", NULL },
! 625: { 0xdb, 0, "FPU exceptions", NULL },
! 626: { 0xdc, 0, "DR0 breakpoint matches", NULL },
! 627: { 0xdd, 0, "DR1 breakpoint matches", NULL },
! 628: { 0xde, 0, "DR2 breakpoint matches", NULL },
! 629: { 0xdf, 0, "DR3 breakpoint matches", NULL },
! 630: { 0xe0, 0, "DRAM accesses", NULL },
! 631: { 0xe1, 0, "Memory controller page tables overflow", NULL },
! 632: { 0xe3, 0, "Memory controller turnarounds", NULL },
! 633: { 0xe4, 0, "Memory controller bypass counter saturation", NULL },
! 634: { 0xe5, 0, "Sized blocks", NULL },
! 635: { 0xe8, 0, "ECC errors", NULL },
! 636: { 0xe9, 0, "CPU/IO requests to memory/IO", NULL },
! 637: { 0xea, 0, "Cache blocks commands", NULL },
! 638: { 0xeb, 0, "Sized commands", NULL },
! 639: { 0xec, 0, "Probe responses and upstream requests", NULL },
! 640: { 0xee, 0, "GART events", NULL },
! 641: { 0xf6, 0, "HT link 0 transmit bandwidth", NULL },
! 642: { 0xf7, 0, "HT link 1 transmit bandwidth", NULL },
! 643: { 0xf8, 0, "HT link 2 transmit bandwidth", NULL },
! 644: { 0x0, 0, NULL, NULL }
! 645: };
! 646:
! 647: #endif /* _PCTRVAR_H_ */
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