Annotation of src/usr.bin/pctr/pctrvar.h, Revision 1.2
1.2 ! deraadt 1: /* $OpenBSD: pctrvar.h,v 1.1 2007/10/17 02:30:23 deraadt Exp $ */
1.1 deraadt 2:
3: /*
4: * Copyright (c) 2007 Mike Belopuhov, Aleksey Lomovtsev
5: *
6: * Permission to use, copy, modify, and distribute this software for any
7: * purpose with or without fee is hereby granted, provided that the above
8: * copyright notice and this permission notice appear in all copies.
9: *
10: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17: */
18:
19: /*
20: * Pentium performance counter control program for OpenBSD.
21: * Copyright 1996 David Mazieres <dm@lcs.mit.edu>.
22: *
23: * Modification and redistribution in source and binary forms is
24: * permitted provided that due credit is given to the author and the
25: * OpenBSD project by leaving this copyright notice intact.
26: */
27:
28: #ifndef _PCTRVAR_H_
29: #define _PCTRVAR_H_
30:
31: #define ARCH_UNDEF 0
32: #define ARCH_I386 1
33: #define ARCH_AMD64 2
34:
35: #define CPU_UNDEF 0
36: #define CPU_P5 1
37: #define CPU_P6 2
38: #define CPU_CORE 3
39: #define CPU_AMD 4
40:
41: #define PCTR_AMD_NUM 4
42: #define PCTR_INTEL_NUM 2 /* Intel supports only 2 counters */
43:
44: #define PCTR_MAX_FUNCT 0xff
45: #define PCTR_MAX_UMASK 0xff
46:
47: #define CFL_MESI 0x01 /* Unit mask accepts MESI encoding */
48: #define CFL_SA 0x02 /* Unit mask accepts Self/Any bit */
49: #define CFL_C0 0x04 /* Counter 0 only */
50: #define CFL_C1 0x08 /* Counter 1 only */
51: #define CFL_ED 0x10 /* Edge detect is needed */
52:
53: /* Pentium defines */
1.2 ! deraadt 54: #ifndef P5CTR_K
! 55: #define P5CTR_K 0x040
! 56: #endif
! 57: #ifndef P5CTR_U
! 58: #define P5CTR_U 0x080
! 59: #endif
! 60: #ifndef P5CTR_C
! 61: #define P5CTR_C 0x100
! 62: #endif
1.1 deraadt 63:
64: struct ctrfn {
65: u_int32_t fn;
66: int flags;
67: char *name;
68: char *desc;
69: };
70:
71: struct ctrfn p5fn[] = {
72: { 0x00, 0, "Data read", NULL },
73: { 0x01, 0, "Data write", NULL },
74: { 0x02, 0, "Data TLB miss", NULL },
75: { 0x03, 0, "Data read miss", NULL },
76: { 0x04, 0, "Data write miss", NULL },
77: { 0x05, 0, "Write (hit) to M or E state lines", NULL },
78: { 0x06, 0, "Data cache lines written back", NULL },
79: { 0x07, 0, "Data cache snoops", NULL },
80: { 0x08, 0, "Data cache snoop hits", NULL },
81: { 0x09, 0, "Memory accesses in both pipes", NULL },
82: { 0x0a, 0, "Bank conflicts", NULL },
83: { 0x0b, 0, "Misaligned data memory references", NULL },
84: { 0x0c, 0, "Code read", NULL },
85: { 0x0d, 0, "Code TLB miss", NULL },
86: { 0x0e, 0, "Code cache miss", NULL },
87: { 0x0f, 0, "Any segment register load", NULL },
88: { 0x12, 0, "Branches", NULL },
89: { 0x13, 0, "BTB hits", NULL },
90: { 0x14, 0, "Taken branch or BTB hit", NULL },
91: { 0x15, 0, "Pipeline flushes", NULL },
92: { 0x16, 0, "Instructions executed", NULL },
93: { 0x17, 0, "Instructions executed in the V-pipe", NULL },
94: { 0x18, 0, "Bus utilization (clocks)", NULL },
95: { 0x19, 0, "Pipeline stalled by write backup", NULL },
96: { 0x1a, 0, "Pipeline stalled by data memory read", NULL },
97: { 0x1b, 0, "Pipeline stalled by write to E or M line", NULL },
98: { 0x1c, 0, "Locked bus cycle", NULL },
99: { 0x1d, 0, "I/O read or write cycle", NULL },
100: { 0x1e, 0, "Noncacheable memory references", NULL },
101: { 0x1f, 0, "AGI (Address Generation Interlock)", NULL },
102: { 0x22, 0, "Floating-point operations", NULL },
103: { 0x23, 0, "Breakpoint 0 match", NULL },
104: { 0x24, 0, "Breakpoint 1 match", NULL },
105: { 0x25, 0, "Breakpoint 2 match", NULL },
106: { 0x26, 0, "Breakpoint 3 match", NULL },
107: { 0x27, 0, "Hardware interrupts", NULL },
108: { 0x28, 0, "Data read or data write", NULL },
109: { 0x29, 0, "Data read miss or data write miss", NULL },
110: { 0x0, 0, NULL, NULL },
111: };
112:
113: struct ctrfn p6fn[] = {
114: { 0x03, 0, "LD_BLOCKS",
115: "Number of store buffer blocks." },
116: { 0x04, 0, "SB_DRAINS",
117: "Number of store buffer drain cycles." },
118: { 0x05, 0, "MISALIGN_MEM_REF",
119: "Number of misaligned data memory references." },
120: { 0x06, 0, "SEGMENT_REG_LOADS",
121: "Number of segment register loads." },
122: { 0x10, CFL_C0, "FP_COMP_OPS_EXE",
123: "Number of computational floating-point operations executed." },
124: { 0x11, CFL_C1, "FP_ASSIST",
125: "Number of floating-point exception cases handled by microcode." },
126: { 0x12, CFL_C1, "MUL",
127: "Number of multiplies." },
128: { 0x13, CFL_C1, "DIV",
129: "Number of divides." },
130: { 0x14, CFL_C0, "CYCLES_DIV_BUSY",
131: "Number of cycles during which the divider is busy." },
132: { 0x21, 0, "L2_ADS",
133: "Number of L2 address strobes." },
134: { 0x22, 0, "L2_DBUS_BUSY",
135: "Number of cycles durring which the data bus was busy." },
136: { 0x23, 0, "L2_DBUS_BUSY_RD",
137: "Number of cycles during which the data bus was busy transferring "
138: "data from L2 to the processor." },
139: { 0x24, 0, "L2_LINES_IN",
140: "Number of lines allocated in the L2." },
141: { 0x25, 0, "L2_M_LINES_INM",
142: "Number of modified lines allocated in the L2." },
143: { 0x26, 0, "L2_LINES_OUT",
144: "Number of lines removed from the L2 for any reason." },
145: { 0x27, 0, "L2_M_LINES_OUTM",
146: "Number of modified lines removed from the L2 for any reason." },
147: { 0x28, CFL_MESI, "L2_IFETCH",
148: "Number of L2 instruction fetches." },
149: { 0x29, CFL_MESI, "L2_LD",
150: "Number of L2 data loads." },
151: { 0x2a, CFL_MESI, "L2_ST",
152: "Number of L2 data stores." },
153: { 0x2e, CFL_MESI, "L2_RQSTS",
154: "Number of L2 requests." },
155: { 0x43, 0, "DATA_MEM_REF",
156: "Number of all memory references, both cacheable and non-cacheable." },
157: { 0x44, 0, "DATA_MEM_CACHE_REF",
158: "Number of L1 data cacheable read and write operations." },
159: { 0x45, 0, "DCU_LINES_IN",
160: "Total lines allocated in the DCU." },
161: { 0x46, 0, "DCU_M_LINES_IN",
162: "Number of M state lines allocated in the DCU." },
163: { 0x47, 0, "DCU_M_LINES_OUT",
164: "Number of M state lines evicted from the DCU. "
165: "This includes evictions via snoop HITM, intervention or replacement" },
166: { 0x48, 0, "DCU_MISS_OUTSTANDING",
167: "Weighted number of cycles while a DCU miss is outstanding." },
168: { 0x60, 0, "BUS_REQ_OUTSTANDING",
169: "Number of bus requests outstanding." },
170: { 0x61, 0, "BUS_BNR_DRV",
171: "Number of bus clock cycles during which the processor is "
172: "driving the BNR pin." },
173: { 0x62, CFL_SA, "BUS_DRDY_CLOCKS",
174: "Number of clocks during which DRDY is asserted." },
175: { 0x63, CFL_SA, "BUS_LOCK_CLOCKS",
176: "Number of clocks during which LOCK is asserted." },
177: { 0x64, 0, "BUS_DATA_RCV",
178: "Number of bus clock cycles during which the processor is "
179: "receiving data." },
180: { 0x65, CFL_SA, "BUS_TRAN_BRD",
181: "Number of burst read transactions." },
182: { 0x66, CFL_SA, "BUS_TRAN_RFO",
183: "Number of read for ownership transactions." },
184: { 0x67, CFL_SA, "BUS_TRANS_WB",
185: "Number of write back transactions." },
186: { 0x68, CFL_SA, "BUS_TRAN_IFETCH",
187: "Number of instruction fetch transactions." },
188: { 0x69, CFL_SA, "BUS_TRAN_INVAL",
189: "Number of invalidate transactions." },
190: { 0x6a, CFL_SA, "BUS_TRAN_PWR",
191: "Number of partial write transactions." },
192: { 0x6b, CFL_SA, "BUS_TRANS_P",
193: "Number of partial transactions." },
194: { 0x6c, CFL_SA, "BUS_TRANS_IO",
195: "Number of I/O transactions." },
196: { 0x6d, CFL_SA, "BUS_TRAN_DEF",
197: "Number of deferred transactions." },
198: { 0x6e, CFL_SA, "BUS_TRAN_BURST",
199: "Number of burst transactions." },
200: { 0x6f, CFL_SA, "BUS_TRAN_MEM",
201: "Number of memory transactions." },
202: { 0x70, CFL_SA, "BUS_TRAN_ANY",
203: "Number of all transactions." },
204: { 0x79, 0, "CPU_CLK_UNHALTED",
205: "Number of cycles during which the processor is not halted." },
206: { 0x7a, 0, "BUS_HIT_DRV",
207: "Number of bus clock cycles during which the processor is "
208: "driving the HIT pin." },
209: { 0x7b, 0, "BUS_HITM_DRV",
210: "Number of bus clock cycles during which the processor is "
211: "driving the HITM pin." },
212: { 0x7e, 0, "BUS_SNOOP_STALL",
213: "Number of clock cycles during which the bus is snoop stalled." },
214: { 0x80, 0, "IFU_IFETCH",
215: "Number of instruction fetches, both cacheable and non-cacheable." },
216: { 0x81, 0, "IFU_IFETCH_MISS",
217: "Number of instruction fetch misses." },
218: { 0x85, 0, "ITLB_MISS",
219: "Number of ITLB misses." },
220: { 0x86, 0, "IFU_MEM_STALL",
221: "Number of cycles that the instruction fetch pipe stage is stalled, "
222: "including cache mises, ITLB misses, ITLB faults, "
223: "and victim cache evictions" },
224: { 0x87, 0, "ILD_STALL",
225: "Number of cycles that the instruction length decoder is stalled" },
226: { 0xa2, 0, "RESOURCE_STALLS",
227: "Number of cycles during which there are resource-related stalls." },
228: { 0xc0, 0, "INST_RETIRED",
229: "Number of instructions retired." },
230: { 0xc1, CFL_C0, "FLOPS",
231: "Number of computational floating-point operations retired." },
232: { 0xc2, 0, "UOPS_RETIRED",
233: "Number of UOPs retired." },
234: { 0xc4, 0, "BR_INST_RETIRED",
235: "Number of branch instructions retired." },
236: { 0xc5, 0, "BR_MISS_PRED_RETIRED",
237: "Number of mispredicted branches retired." },
238: { 0xc6, 0, "CYCLES_INT_MASKED",
239: "Number of processor cycles for which interrupts are disabled." },
240: { 0xc7, 0, "CYCLES_INT_PENDING_AND_MASKED",
241: "Number of processor cycles for which interrupts are disabled "
242: "and interrupts are pending." },
243: { 0xc8, 0, "HW_INT_RX",
244: "Number of hardware interrupts received." },
245: { 0xc9, 0, "BR_TAKEN_RETIRED",
246: "Number of taken branches retired." },
247: { 0xca, 0, "BR_MISS_PRED_TAKEN_RET",
248: "Number of taken mispredictioned branches retired." },
249: { 0xd0, 0, "INST_DECODER",
250: "Number of instructions decoded." },
251: { 0xd2, 0, "PARTIAL_RAT_STALLS",
252: "Number of cycles or events for partial stalls." },
253: { 0xe0, 0, "BR_INST_DECODED",
254: "Number of branch instructions decoded." },
255: { 0xe2, 0, "BTB_MISSES",
256: "Number of branches that miss the BTB." },
257: { 0xe4, 0, "BR_BOGUS",
258: "Number of bogus branches." },
259: { 0xe6, 0, "BACLEARS",
260: "Number of times BACLEAR is asserted." },
261: { 0x0, 0, NULL, NULL}
262: };
263:
264: struct ctrfn corefn[] = {
265: { 0x03, 0, "LD_BLOCKS",
266: "Number of store buffer blocks." },
267: { 0x04, 0, "SB_DRAINS",
268: "Number of store buffer drain cycles." },
269: { 0x06, 0, "SEGMENT_REG_LOADS",
270: "Number of segment register loads." },
271: { 0x07, 0, "SSE_PRE_EXEC",
272: "Streaming SIMD Extensions Prefetch NTA instructions executed" },
273: { 0x08, 0, "DTLB_MISSES",
274: "Memory accesses missed the DTLB" },
275: { 0x09, 0, "MEMORY_DISAMBIGUATION",
276: "Memory disambiguation reset cycles" },
277: { 0x0c, 0, "PAGE_WALKS",
278: "Number of page-walks executed" },
279: { 0x10, 0, "FP_COMP_OPS_EXE",
280: "Floating point computational micro-ops executed" },
281: { 0x11, 0, "FP_ASSIST",
282: "Number of floating-point exception cases handled by microcode." },
283: { 0x12, 0, "MUL",
284: "Number of multiplies." },
285: { 0x13, 0, "DIV",
286: "Number of divides." },
287: { 0x14, 0, "CYCLES_DIV_BUSY",
288: "Number of cycles during which the divider is busy." },
289: { 0x18, 0, "IDLE_DURING_DIV",
290: "Cycles the divider is busy and all other execution units are idle." },
291: { 0x19, 0, "DELAYED_BYPASS",
292: "Delayed bypass to FP operation." },
293: { 0x21, 0, "L2_ADS",
294: "Number of L2 address strobes." },
295: { 0x23, 0, "L2_DBUS_BUSY_RD",
296: "Number of cycles during which the data bus was busy transferring "
297: "data from L2 to the core."},
298: { 0x24, 0, "L2_LINES_IN",
299: "Number of lines allocated in the L2 (L2 cache misses.)" },
300: { 0x25, 0, "L2_M_LINES_INM",
301: "Number of modified lines allocated in the L2." },
302: { 0x26, 0, "L2_LINES_OUT",
303: "Number of lines removed from the L2 for any reason." },
304: { 0x27, 0, "L2_M_LINES_OUTM",
305: "Number of modified lines removed from the L2 for any reason." },
306: { 0x28, CFL_MESI, "L2_IFETCH",
307: "Number of L2 instruction fetches." },
308: { 0x29, CFL_MESI, "L2_LD",
309: "Number of L2 data loads." },
310: { 0x2a, CFL_MESI, "L2_ST",
311: "Number of L2 data stores." },
312: { 0x2e, CFL_MESI, "L2_RQSTS",
313: "Number of L2 requests." },
314: { 0x30, CFL_MESI, "L2_REJECT_CYCLES",
315: "Number of cycles L2 is busy and rejecting new requests." },
316: { 0x32, CFL_MESI, "L2_NO_REQUEST_CYCLES",
317: "Number of cycles there is no request to access L2." },
318: { 0x3a, 0, "EST_TRANS_ALL",
319: "Number of any Intel Enhanced SpeedStep Technology transitions." },
320: { 0x3b, CFL_ED, "THERMAL_TRIP",
321: "Duration in a thermal trip based on the current core clock." },
322: { 0x3c, 0, "NONHLT_REF_CYCLES",
323: "Number of non-halted bus cycles." },
324: { 0x40, CFL_MESI, "L1D_CACHE_LD",
325: "L1 cacheable data reads." },
326: { 0x41, CFL_MESI, "L1D_CACHE_ST",
327: "L1 cacheable data writes." },
328: { 0x42, CFL_MESI, "L1D_CACHE_LOCK",
329: "L1 data cacheable locked reads." },
330: { 0x43, 0, "L1D_ALL_REF",
331: "All memory references to the L1 DCACHE."},
332: { 0x45, 0, "L1D_REPL",
333: "Total lines allocated in the L1 DCACHE." },
334: { 0x46, 0, "L1D_M_REPL",
335: "Number of M state lines allocated in the L1 DCACHE." },
336: { 0x47, 0, "L1D_M_EVICT",
337: "Number of M state lines evicted from the L1 DCACHE. "
338: "This includes evictions via snoop HITM, intervention or "
339: "replacement." },
340: { 0x48, 0, "L1D_PEND_MISS",
341: "Total number of outstanding L1 data cache misses at any cycle." },
342: { 0x49, 0, "DTLB_MISS",
343: "Number of data references that missed TLB." },
344: { 0x4b, 0, "SSE_PRE_MISS",
345: "Number of cache misses by the SSE Prefetch NTA instructions." },
346: { 0x4c, 0, "LOAD_HIT_PRE",
347: "Load operations conflicting with a software prefetch." },
348: { 0x4e, 0, "L1D_PREFETCH",
349: "L1 DCACHE prefetch requests" },
350: { 0x4f, 0, "L1_PREF_REQ",
351: "Number of L1 prefetch requests due to DCU cache misse.s" },
352: { 0x60, CFL_SA, "BUS_REQ_OUTSTANDING",
353: "Number of bus requests outstanding." },
354: { 0x61, CFL_SA, "BUS_BNR_DRV",
355: "Number of bus clock cycles during which the processor is "
356: "driving the BNR pin." },
357: { 0x62, CFL_SA, "BUS_DRDY_CLOCKS",
358: "Number of clocks during which DRDY is asserted." },
359: { 0x63, CFL_SA, "BUS_LOCK_CLOCKS",
360: "Number of clocks during which LOCK is asserted." },
361: { 0x64, 0, "BUS_DATA_RCV",
362: "Number of bus clock cycles during which the processor is "
363: "receiving data." },
364: { 0x65, CFL_SA, "BUS_TRAN_BRD",
365: "Number of burst read transactions." },
366: { 0x66, CFL_SA, "BUS_TRAN_RFO",
367: "Number of read for ownership transactions." },
368: { 0x67, CFL_SA, "BUS_TRANS_WB",
369: "Number of write back transactions." },
370: { 0x68, CFL_SA, "BUS_TRAN_IFETCH",
371: "Number of instruction fetch transactions." },
372: { 0x69, CFL_SA, "BUS_TRAN_INVAL",
373: "Number of invalidate transactions." },
374: { 0x6a, CFL_SA, "BUS_TRAN_PWR",
375: "Number of partial write transactions." },
376: { 0x6b, CFL_SA, "BUS_TRANS_P",
377: "Number of partial transactions." },
378: { 0x6c, CFL_SA, "BUS_TRANS_IO",
379: "Number of I/O transactions." },
380: { 0x6d, CFL_SA, "BUS_TRAN_DEF",
381: "Number of deferred transactions." },
382: { 0x6e, CFL_SA, "BUS_TRAN_BURST",
383: "Number of burst transactions." },
384: { 0x6f, CFL_SA, "BUS_TRAN_MEM",
385: "Number of memory transactions." },
386: { 0x70, CFL_SA, "BUS_TRAN_ANY",
387: "Number of all transactions." },
388: { 0x77, CFL_MESI, "BUS_SNOOPS",
389: "Number of external bus cycles while bus lock signal asserted." },
390: { 0x78, 0, "CMP_SNOOP",
391: "Number of L1 DCACHE snoops by other core." },
392: { 0x7a, CFL_SA, "BUS_HIT_DRV",
393: "Number of bus clock cycles during which the processor is "
394: "driving the HIT pin." },
395: { 0x7b, CFL_SA, "BUS_HITM_DRV",
396: "Number of bus clock cycles during which the processor is "
397: "driving the HITM pin." },
398: { 0x7d, CFL_SA, "BUS_NOT_IN_USE",
399: "Number of cycles there is no transaction from the core." },
400: { 0x7e, CFL_SA, "SNOOP_STALL_DRV",
401: "Number of clock cycles during which the bus is snoop stalled." },
402: { 0x7f, 0, "BUS_IO_WAIT",
403: "Number of cycles during which IO requests wait int the bus queue." },
404: { 0x80, 0, "L1I_READS",
405: "Number of instruction fetches, both cacheable and non-cacheable." },
406: { 0x81, 0, "L1I_MISSES",
407: "Number of instruction fetch misses." },
408: { 0x82, 0, "ITLB_MISS",
409: "Number of ITLB misses." },
410: { 0x83, 0, "INSQ_QUEUE",
411: "Cycles during which the instruction queue is full." },
412: { 0x85, 0, "ITLB_MISSES",
413: "Number of ITLB misses." },
414: { 0x86, 0, "CYCLES_L1I_MEM_STALLED",
415: "Number of cycles that the instruction fetches stalled, "
416: "including cache mises, ITLB misses, ITLB faults, "
417: "and victim cache evictions" },
418: { 0x87, 0, "ILD_STALL",
419: "Number of cycles that the instruction length decoder is stalled." },
420: { 0x88, 0, "BR_INST_EXEC",
421: "Number of branch instructions executed." },
422: { 0x89, 0, "BR_MISSP_EXEC",
423: "Number of mispredicted branch instructions that were executed." },
424: { 0x8a, 0, "BR_BAC_MISSP_EXEC",
425: "Number of branch instructions that were mispredicted at decoding." },
426: { 0x8b, 0, "BR_CND_EXEC",
427: "Number of conditional branch instructions executed, but not "
428: "necessarily retired." },
429: { 0x8c, 0, "BR_CND_MISSP_EXEC",
430: "Number of mispredicted conditional branch instructions that "
431: "were executed." },
432: { 0x8d, 0, "BR_IND_EXEC",
433: "Number of indirect branch instructions that were executed." },
434: { 0x8e, 0, "BR_IND_MISSP_EXEC",
435: "number of mispredicted indirect branch instructions that were "
436: "executed." },
437: { 0x8f, 0, "BR_RET_EXEC",
438: "Number of RET instructions that were executed." },
439: { 0x90, 0, "BR_RET_MISSP_EXEC",
440: "Number of mispredicted RET instructions that were executed." },
441: { 0x91, 0, "BR_RET_BAC_MISSP_EXEC",
442: "Number of RET instructions that were executed and were mispredicted "
443: "at decoding." },
444: { 0x92, 0, "BR_CALL_EXEC",
445: "Number of CALL instructions executed." },
446: { 0x93, 0, "BR_CALL_MISSP_EXEC",
447: "Number of mispredicted CALL instructions that were executed." },
448: { 0x94, 0, "BR_IND_CALL_EXEC",
449: "Number of indirect CALL instructions that were executed." },
450: { 0x97, 0, "BR_TKN_BUBBLE_1",
451: "Number of times a taken branch predicted taken with bubble 1." },
452: { 0x98, 0, "BR_TKN_BUBBLE_2",
453: "Number of times a taken branch predicted taken with bubble 2." },
454: { 0xa0, 0, "RS_UOPS_DISPATCHED",
455: "Number of microops dispatched for execution." },
456: { 0xa2, 0, "RESOURCE_STALL",
457: "Number of cycles while there us a resource related stall." },
458: { 0xaa, 0, "MACRO_INSTS",
459: "Number of instructions decoded (but not necessarily executed "
460: "or retired)." },
461: { 0xab, 0, "ESP",
462: "ESP register operations." },
463: { 0xb0, 0, "SIMD_UOPS_EXEC",
464: "Number of SIMD micro-ops executed (excluding stores)." },
465: { 0xb1, 0, "SIMD_SAT_UOP_EXEC",
466: "Number of SIMD saturated arithmetic micro-ops executed." },
467: { 0xb3, 0, "SIMD_UOP_TYPE_EXEC",
468: "Number of SIMD packed multiply micro-ops executed." },
469: { 0xc0, 0, "INST_RETIRED",
470: "Number of instructions retired." },
471: { 0xc1, 0, "X87_OPS_RETIRED",
472: "Number of computational floating-point operations retired." },
473: { 0xc2, 0, "UOPS_RETIRED",
474: "Number of UOPs retired." },
475: { 0xc3, 0, "MACHINE_NUKES",
476: "Number of times the pipeline is restarted due to either "
477: "multithreaded memory ordering conflicts or memory disambiguation "
478: "misprediction." },
479: { 0xc4, 0, "BR_INST_RETIRED",
480: "Number of branch instructions retired." },
481: { 0xc5, 0, "BR_MISS_PRED_RETIRED",
482: "Number of mispredicted branches retired." },
483: { 0xc6, 0, "CYCLES_INT_MASKED",
484: "Number of processor cycles for which interrupts are disabled." },
485: { 0xc7, 0, "SIMD_INST_RETIRED",
486: "Number of SSE instructions retired." },
487: { 0xc8, 0, "HW_INT_RCV",
488: "Number of hardware interrupts received." },
489: { 0xc9, 0, "ITLB_MISS_RETIRED",
490: "Number of retired instructions that missed the ITLB when they "
491: "were fetched."},
492: { 0xca, 0, "SIMD_COMP_INST_RETIRED",
493: "Number of computational SSE instructions retired." },
494: { 0xcb, 0, "MEM_LOAD_RETIRED",
495: "Number of retired load operations that missed the L1 DCACHE." },
496: { 0xcc, 0, "FP_MMX_TRANS_TO_MMX",
497: "Number of the first MMX instructions following a floating-point "
498: "instruction." },
499: { 0xcd, 0, "SIMD_ASSIST",
500: "Number of SIMD assists invoked." },
501: { 0xce, 0, "SIMD_INSTR_RETIRED",
502: "Number of SIMD instructions that retired." },
503: { 0xcf, 0, "SIMD_SAT_INSTR_RETIRED",
504: "Number of saturated arithmetic SIMD instructions that retired." },
505: { 0xd0, 0, "INSTR_DECODED",
506: "Number of instructions decoded." },
507: { 0xd2, 0, "RAT_STALLS",
508: "Number of cycles or events for partial stalls." },
509: { 0xd4, 0, "SEG_RENAME_STALLS",
510: "Number of stalls due to the lack of renaming resources." },
511: { 0xd5, 0, "SEG_REG_RENAMES",
512: "Number of times the segment register is renamed." },
513: { 0xd7, 0, "ESP_UOPS",
514: "Number of ESP folding instruction decoded." },
515: { 0xd8, 0, "SIMD_FD_RET",
516: "Number of SSE/SSE2 instructions retired." },
517: { 0xd9, 0, "SIMD_FP_COM_RET",
518: "Number of SSE/SSE2 compute instructions retired." },
519: { 0xda, 0, "FUSED_UOPS_RET",
520: "Number of all fused uops retired." },
521: { 0xdb, 0, "UNFUSION",
522: "Number of all unfusion events in the ROB." },
523: { 0xdc, 0, "RESOURCE_STALLS",
524: "Number of cycles when the number of instructions in the pipeline "
525: "waiting for retirement reaches the limit the processor can handle." },
526: { 0xe0, 0, "BR_INST_DECODED",
527: "Number of branch instructions decoded." },
528: { 0xe2, 0, "BTB_MISSES",
529: "Number of branches the BTB did not produce a prediction." },
530: { 0xe4, 0, "BOGUS_BR",
531: "Number of byte sequences that were mistakenly detected as taken "
532: "branch instructions." },
533: { 0xe6, 0, "BACLEARS",
534: "Number of times BACLEAR is asserted." },
535: { 0xf0, 0, "PREF_RQSTS_UP",
536: "Number of upward prefetches issued from the Data Prefetch Logic "
537: "(DPL) to the L2 cache." },
538: { 0xf8, 0, "PREF_RQSTS_DN",
539: "Number of downward prefetches issued from the Data Prefetch Logic "
540: "(DPL) to the L2 cache." },
541: { 0x0, 0, NULL, NULL }
542: };
543:
544: struct ctrfn amdfn[] = {
545: { 0x00, 0, "Dispatched FPU operations", NULL },
546: { 0x01, 0, "Cycles with no FPU ops retired", NULL },
547: { 0x02, 0, "Dispatched fast flag FPU operations", NULL },
548: { 0x20, 0, "Segment register loads", NULL },
549: { 0x21, 0, "Pipeline restart due to self-modifying code", NULL },
550: { 0x22, 0, "Pipeline restart due to probe hit", NULL },
551: { 0x23, 0, "LS2 buffer is full", NULL },
552: { 0x24, 0, "Locked operations", NULL },
553: { 0x26, 0, "Retired CFLUSH instructions", NULL },
554: { 0x27, 0, "Retired CPUID instructions", NULL },
555: { 0x40, 0, "Data cache accesses", NULL },
556: { 0x41, 0, "Data cache misses", NULL },
557: { 0x42, 0, "Data cache refills from L2 or system", NULL },
558: { 0x43, 0, "Data cache refills from system", NULL },
559: { 0x44, 0, "Data cache lines evicted", NULL },
560: { 0x45, 0, "L1 DTLB miss and L2 DTLB hit", NULL },
561: { 0x46, 0, "L1 DTLB miss and L2 DTLB miss", NULL },
562: { 0x47, 0, "Misaligned access", NULL },
563: { 0x48, 0, "Microarchitectural late cancel of an access", NULL },
564: { 0x49, 0, "Microarchitectural early cancel of an access", NULL },
565: { 0x4a, 0, "Single bit ECC errors recorded by scrubber", NULL },
566: { 0x4b, 0, "Prefetch instructions dispatched", NULL },
567: { 0x4c, 0, "DCACHE misses by locked instructions", NULL },
568: { 0x65, 0, "Memory requests by type", NULL },
569: { 0x67, 0, "Data prefetcher", NULL },
570: { 0x6c, 0, "System read responses by coherency state", NULL },
571: { 0x6d, 0, "Quadwords written to system", NULL },
572: { 0x76, 0, "CPU clocks not halted", NULL },
573: { 0x7d, 0, "Requests to L2 cache", NULL },
574: { 0x7e, 0, "L2 cache misses", NULL },
575: { 0x7f, 0, "L2 cache fill/writeback", NULL },
576: { 0x80, 0, "ICACHE fetches", NULL },
577: { 0x81, 0, "ICACHE misses", NULL },
578: { 0x82, 0, "ICACHE refills from L2", NULL },
579: { 0x83, 0, "ICACHE refills from system", NULL },
580: { 0x84, 0, "L1 ITLB miss and L2 ITLB hit", NULL },
581: { 0x85, 0, "L1 ITLB miss and L2 ITLB miss", NULL },
582: { 0x86, 0, "Pipeline restart due to instruction stream probe", NULL },
583: { 0x87, 0, "Instruction fetch stall", NULL },
584: { 0x88, 0, "Return stack hits", NULL },
585: { 0x89, 0, "Return stack overflows", NULL },
586: { 0xc0, 0, "Retired instructions", NULL },
587: { 0xc1, 0, "Retired microops", NULL },
588: { 0xc2, 0, "Retired branch instructions", NULL },
589: { 0xc3, 0, "Retired mispredicted branch instructions", NULL },
590: { 0xc4, 0, "Retired taken branch instructions", NULL },
591: { 0xc5, 0, "Retired mispredicted taken branch instructions", NULL },
592: { 0xc6, 0, "Retired far control transfers", NULL },
593: { 0xc7, 0, "Retired branch resyncs", NULL },
594: { 0xc8, 0, "Retired near returns", NULL },
595: { 0xc9, 0, "Retired mispredicted near returns", NULL },
596: { 0xca, 0, "Retired mispredicted indirect brnaches", NULL },
597: { 0xcb, 0, "Retired MMX/FP instructions", NULL },
598: { 0xcc, 0, "Retired fastpath double op instructions", NULL },
599: { 0xcd, 0, "Interrupts-masked cycles", NULL },
600: { 0xce, 0, "Interrupts-masked cycles with interrupts pending", NULL },
601: { 0xcf, 0, "Interrupts taken", NULL },
602: { 0xd0, 0, "Decoder empty", NULL },
603: { 0xd1, 0, "Dispatch stalls", NULL },
604: { 0xd2, 0, "Dispatch stalls for branch abort retire", NULL },
605: { 0xd3, 0, "Dispatch stalls for serialisation", NULL },
606: { 0xd4, 0, "Dispatch stalls for segment load", NULL },
607: { 0xd5, 0, "Dispatch stalls for reoder buffer full", NULL },
608: { 0xd6, 0, "Dispatch stalls for reservation station full", NULL },
609: { 0xd7, 0, "Dispatch stalls for FPU full", NULL },
610: { 0xd8, 0, "Dispatch stalls for LS full", NULL },
611: { 0xd9, 0, "Dispatch stalls waiting for all quite", NULL },
612: { 0xda, 0, "Dispatch stalls for far transfer or resync to retire", NULL },
613: { 0xdb, 0, "FPU exceptions", NULL },
614: { 0xdc, 0, "DR0 breakpoint matches", NULL },
615: { 0xdd, 0, "DR1 breakpoint matches", NULL },
616: { 0xde, 0, "DR2 breakpoint matches", NULL },
617: { 0xdf, 0, "DR3 breakpoint matches", NULL },
618: { 0xe0, 0, "DRAM accesses", NULL },
619: { 0xe1, 0, "Memory controller page tables overflow", NULL },
620: { 0xe3, 0, "Memory controller turnarounds", NULL },
621: { 0xe4, 0, "Memory controller bypass counter saturation", NULL },
622: { 0xe5, 0, "Sized blocks", NULL },
623: { 0xe8, 0, "ECC errors", NULL },
624: { 0xe9, 0, "CPU/IO requests to memory/IO", NULL },
625: { 0xea, 0, "Cache blocks commands", NULL },
626: { 0xeb, 0, "Sized commands", NULL },
627: { 0xec, 0, "Probe responses and upstream requests", NULL },
628: { 0xee, 0, "GART events", NULL },
629: { 0xf6, 0, "HT link 0 transmit bandwidth", NULL },
630: { 0xf7, 0, "HT link 1 transmit bandwidth", NULL },
631: { 0xf8, 0, "HT link 2 transmit bandwidth", NULL },
632: { 0x0, 0, NULL, NULL }
633: };
634:
635: #endif /* _PCTRVAR_H_ */
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