Annotation of src/usr.bin/pctr/pctrvar.h, Revision 1.3
1.3 ! mikeb 1: /* $OpenBSD: pctrvar.h,v 1.2 2007/10/17 14:54:30 deraadt Exp $ */
1.1 deraadt 2:
3: /*
4: * Copyright (c) 2007 Mike Belopuhov, Aleksey Lomovtsev
5: *
6: * Permission to use, copy, modify, and distribute this software for any
7: * purpose with or without fee is hereby granted, provided that the above
8: * copyright notice and this permission notice appear in all copies.
9: *
10: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17: */
18:
19: /*
20: * Pentium performance counter control program for OpenBSD.
21: * Copyright 1996 David Mazieres <dm@lcs.mit.edu>.
22: *
23: * Modification and redistribution in source and binary forms is
24: * permitted provided that due credit is given to the author and the
25: * OpenBSD project by leaving this copyright notice intact.
26: */
27:
28: #ifndef _PCTRVAR_H_
29: #define _PCTRVAR_H_
30:
31: #define ARCH_UNDEF 0
32: #define ARCH_I386 1
33: #define ARCH_AMD64 2
34:
35: #define CPU_UNDEF 0
36: #define CPU_P5 1
37: #define CPU_P6 2
38: #define CPU_CORE 3
39: #define CPU_AMD 4
40:
41: #define PCTR_AMD_NUM 4
42: #define PCTR_INTEL_NUM 2 /* Intel supports only 2 counters */
43:
44: #define PCTR_MAX_FUNCT 0xff
45: #define PCTR_MAX_UMASK 0xff
46:
47: #define CFL_MESI 0x01 /* Unit mask accepts MESI encoding */
48: #define CFL_SA 0x02 /* Unit mask accepts Self/Any bit */
49: #define CFL_C0 0x04 /* Counter 0 only */
50: #define CFL_C1 0x08 /* Counter 1 only */
51: #define CFL_ED 0x10 /* Edge detect is needed */
1.3 ! mikeb 52: #define CFL_UM 0x20 /* Unit mask is mandatory */
1.1 deraadt 53:
54: /* Pentium defines */
1.2 deraadt 55: #ifndef P5CTR_K
56: #define P5CTR_K 0x040
57: #endif
58: #ifndef P5CTR_U
59: #define P5CTR_U 0x080
60: #endif
61: #ifndef P5CTR_C
62: #define P5CTR_C 0x100
63: #endif
1.1 deraadt 64:
65: struct ctrfn {
66: u_int32_t fn;
67: int flags;
68: char *name;
69: char *desc;
70: };
71:
72: struct ctrfn p5fn[] = {
73: { 0x00, 0, "Data read", NULL },
74: { 0x01, 0, "Data write", NULL },
75: { 0x02, 0, "Data TLB miss", NULL },
76: { 0x03, 0, "Data read miss", NULL },
77: { 0x04, 0, "Data write miss", NULL },
78: { 0x05, 0, "Write (hit) to M or E state lines", NULL },
79: { 0x06, 0, "Data cache lines written back", NULL },
80: { 0x07, 0, "Data cache snoops", NULL },
81: { 0x08, 0, "Data cache snoop hits", NULL },
82: { 0x09, 0, "Memory accesses in both pipes", NULL },
83: { 0x0a, 0, "Bank conflicts", NULL },
84: { 0x0b, 0, "Misaligned data memory references", NULL },
85: { 0x0c, 0, "Code read", NULL },
86: { 0x0d, 0, "Code TLB miss", NULL },
87: { 0x0e, 0, "Code cache miss", NULL },
88: { 0x0f, 0, "Any segment register load", NULL },
89: { 0x12, 0, "Branches", NULL },
90: { 0x13, 0, "BTB hits", NULL },
91: { 0x14, 0, "Taken branch or BTB hit", NULL },
92: { 0x15, 0, "Pipeline flushes", NULL },
93: { 0x16, 0, "Instructions executed", NULL },
94: { 0x17, 0, "Instructions executed in the V-pipe", NULL },
95: { 0x18, 0, "Bus utilization (clocks)", NULL },
96: { 0x19, 0, "Pipeline stalled by write backup", NULL },
97: { 0x1a, 0, "Pipeline stalled by data memory read", NULL },
98: { 0x1b, 0, "Pipeline stalled by write to E or M line", NULL },
99: { 0x1c, 0, "Locked bus cycle", NULL },
100: { 0x1d, 0, "I/O read or write cycle", NULL },
101: { 0x1e, 0, "Noncacheable memory references", NULL },
102: { 0x1f, 0, "AGI (Address Generation Interlock)", NULL },
103: { 0x22, 0, "Floating-point operations", NULL },
104: { 0x23, 0, "Breakpoint 0 match", NULL },
105: { 0x24, 0, "Breakpoint 1 match", NULL },
106: { 0x25, 0, "Breakpoint 2 match", NULL },
107: { 0x26, 0, "Breakpoint 3 match", NULL },
108: { 0x27, 0, "Hardware interrupts", NULL },
109: { 0x28, 0, "Data read or data write", NULL },
110: { 0x29, 0, "Data read miss or data write miss", NULL },
111: { 0x0, 0, NULL, NULL },
112: };
113:
114: struct ctrfn p6fn[] = {
115: { 0x03, 0, "LD_BLOCKS",
116: "Number of store buffer blocks." },
117: { 0x04, 0, "SB_DRAINS",
118: "Number of store buffer drain cycles." },
119: { 0x05, 0, "MISALIGN_MEM_REF",
120: "Number of misaligned data memory references." },
121: { 0x06, 0, "SEGMENT_REG_LOADS",
122: "Number of segment register loads." },
123: { 0x10, CFL_C0, "FP_COMP_OPS_EXE",
124: "Number of computational floating-point operations executed." },
125: { 0x11, CFL_C1, "FP_ASSIST",
126: "Number of floating-point exception cases handled by microcode." },
127: { 0x12, CFL_C1, "MUL",
128: "Number of multiplies." },
129: { 0x13, CFL_C1, "DIV",
130: "Number of divides." },
131: { 0x14, CFL_C0, "CYCLES_DIV_BUSY",
132: "Number of cycles during which the divider is busy." },
133: { 0x21, 0, "L2_ADS",
134: "Number of L2 address strobes." },
135: { 0x22, 0, "L2_DBUS_BUSY",
136: "Number of cycles durring which the data bus was busy." },
137: { 0x23, 0, "L2_DBUS_BUSY_RD",
138: "Number of cycles during which the data bus was busy transferring "
139: "data from L2 to the processor." },
140: { 0x24, 0, "L2_LINES_IN",
141: "Number of lines allocated in the L2." },
142: { 0x25, 0, "L2_M_LINES_INM",
143: "Number of modified lines allocated in the L2." },
144: { 0x26, 0, "L2_LINES_OUT",
145: "Number of lines removed from the L2 for any reason." },
146: { 0x27, 0, "L2_M_LINES_OUTM",
147: "Number of modified lines removed from the L2 for any reason." },
148: { 0x28, CFL_MESI, "L2_IFETCH",
149: "Number of L2 instruction fetches." },
150: { 0x29, CFL_MESI, "L2_LD",
151: "Number of L2 data loads." },
152: { 0x2a, CFL_MESI, "L2_ST",
153: "Number of L2 data stores." },
154: { 0x2e, CFL_MESI, "L2_RQSTS",
155: "Number of L2 requests." },
156: { 0x43, 0, "DATA_MEM_REF",
157: "Number of all memory references, both cacheable and non-cacheable." },
158: { 0x44, 0, "DATA_MEM_CACHE_REF",
159: "Number of L1 data cacheable read and write operations." },
160: { 0x45, 0, "DCU_LINES_IN",
161: "Total lines allocated in the DCU." },
162: { 0x46, 0, "DCU_M_LINES_IN",
163: "Number of M state lines allocated in the DCU." },
164: { 0x47, 0, "DCU_M_LINES_OUT",
165: "Number of M state lines evicted from the DCU. "
166: "This includes evictions via snoop HITM, intervention or replacement" },
167: { 0x48, 0, "DCU_MISS_OUTSTANDING",
168: "Weighted number of cycles while a DCU miss is outstanding." },
169: { 0x60, 0, "BUS_REQ_OUTSTANDING",
170: "Number of bus requests outstanding." },
171: { 0x61, 0, "BUS_BNR_DRV",
172: "Number of bus clock cycles during which the processor is "
173: "driving the BNR pin." },
174: { 0x62, CFL_SA, "BUS_DRDY_CLOCKS",
175: "Number of clocks during which DRDY is asserted." },
176: { 0x63, CFL_SA, "BUS_LOCK_CLOCKS",
177: "Number of clocks during which LOCK is asserted." },
178: { 0x64, 0, "BUS_DATA_RCV",
179: "Number of bus clock cycles during which the processor is "
180: "receiving data." },
181: { 0x65, CFL_SA, "BUS_TRAN_BRD",
182: "Number of burst read transactions." },
183: { 0x66, CFL_SA, "BUS_TRAN_RFO",
184: "Number of read for ownership transactions." },
185: { 0x67, CFL_SA, "BUS_TRANS_WB",
186: "Number of write back transactions." },
187: { 0x68, CFL_SA, "BUS_TRAN_IFETCH",
188: "Number of instruction fetch transactions." },
189: { 0x69, CFL_SA, "BUS_TRAN_INVAL",
190: "Number of invalidate transactions." },
191: { 0x6a, CFL_SA, "BUS_TRAN_PWR",
192: "Number of partial write transactions." },
193: { 0x6b, CFL_SA, "BUS_TRANS_P",
194: "Number of partial transactions." },
195: { 0x6c, CFL_SA, "BUS_TRANS_IO",
196: "Number of I/O transactions." },
197: { 0x6d, CFL_SA, "BUS_TRAN_DEF",
198: "Number of deferred transactions." },
199: { 0x6e, CFL_SA, "BUS_TRAN_BURST",
200: "Number of burst transactions." },
201: { 0x6f, CFL_SA, "BUS_TRAN_MEM",
202: "Number of memory transactions." },
203: { 0x70, CFL_SA, "BUS_TRAN_ANY",
204: "Number of all transactions." },
205: { 0x79, 0, "CPU_CLK_UNHALTED",
206: "Number of cycles during which the processor is not halted." },
207: { 0x7a, 0, "BUS_HIT_DRV",
208: "Number of bus clock cycles during which the processor is "
209: "driving the HIT pin." },
210: { 0x7b, 0, "BUS_HITM_DRV",
211: "Number of bus clock cycles during which the processor is "
212: "driving the HITM pin." },
213: { 0x7e, 0, "BUS_SNOOP_STALL",
214: "Number of clock cycles during which the bus is snoop stalled." },
215: { 0x80, 0, "IFU_IFETCH",
216: "Number of instruction fetches, both cacheable and non-cacheable." },
217: { 0x81, 0, "IFU_IFETCH_MISS",
218: "Number of instruction fetch misses." },
219: { 0x85, 0, "ITLB_MISS",
220: "Number of ITLB misses." },
221: { 0x86, 0, "IFU_MEM_STALL",
222: "Number of cycles that the instruction fetch pipe stage is stalled, "
223: "including cache mises, ITLB misses, ITLB faults, "
224: "and victim cache evictions" },
225: { 0x87, 0, "ILD_STALL",
226: "Number of cycles that the instruction length decoder is stalled" },
227: { 0xa2, 0, "RESOURCE_STALLS",
228: "Number of cycles during which there are resource-related stalls." },
229: { 0xc0, 0, "INST_RETIRED",
230: "Number of instructions retired." },
231: { 0xc1, CFL_C0, "FLOPS",
232: "Number of computational floating-point operations retired." },
233: { 0xc2, 0, "UOPS_RETIRED",
234: "Number of UOPs retired." },
235: { 0xc4, 0, "BR_INST_RETIRED",
236: "Number of branch instructions retired." },
237: { 0xc5, 0, "BR_MISS_PRED_RETIRED",
238: "Number of mispredicted branches retired." },
239: { 0xc6, 0, "CYCLES_INT_MASKED",
240: "Number of processor cycles for which interrupts are disabled." },
241: { 0xc7, 0, "CYCLES_INT_PENDING_AND_MASKED",
242: "Number of processor cycles for which interrupts are disabled "
243: "and interrupts are pending." },
244: { 0xc8, 0, "HW_INT_RX",
245: "Number of hardware interrupts received." },
246: { 0xc9, 0, "BR_TAKEN_RETIRED",
247: "Number of taken branches retired." },
248: { 0xca, 0, "BR_MISS_PRED_TAKEN_RET",
249: "Number of taken mispredictioned branches retired." },
250: { 0xd0, 0, "INST_DECODER",
251: "Number of instructions decoded." },
252: { 0xd2, 0, "PARTIAL_RAT_STALLS",
253: "Number of cycles or events for partial stalls." },
254: { 0xe0, 0, "BR_INST_DECODED",
255: "Number of branch instructions decoded." },
256: { 0xe2, 0, "BTB_MISSES",
257: "Number of branches that miss the BTB." },
258: { 0xe4, 0, "BR_BOGUS",
259: "Number of bogus branches." },
260: { 0xe6, 0, "BACLEARS",
261: "Number of times BACLEAR is asserted." },
262: { 0x0, 0, NULL, NULL}
263: };
264:
265: struct ctrfn corefn[] = {
266: { 0x03, 0, "LD_BLOCKS",
267: "Number of store buffer blocks." },
1.3 ! mikeb 268: { 0x04, 0, "SD_DRAIN",
1.1 deraadt 269: "Number of store buffer drain cycles." },
1.3 ! mikeb 270: { 0x05, 0, "MISALIGN_MEM_REF",
! 271: "Number of misaligned data memory references." },
! 272: { 0x06, 0, "SEG_REG_LOADS",
1.1 deraadt 273: "Number of segment register loads." },
1.3 ! mikeb 274: { 0x07, 0, "SSE_PREF_RET",
! 275: "SSE software prefetch instructions retired." },
! 276: { 0x08, CFL_UM, "DTLB_MISSES",
1.1 deraadt 277: "Memory accesses missed the DTLB" },
1.3 ! mikeb 278: { 0x09, CFL_UM, "MEMORY_DISAMBIGUATION",
1.1 deraadt 279: "Memory disambiguation reset cycles" },
1.3 ! mikeb 280: { 0x0c, CFL_UM, "PAGE_WALKS",
1.1 deraadt 281: "Number of page-walks executed" },
282: { 0x10, 0, "FP_COMP_OPS_EXE",
283: "Floating point computational micro-ops executed" },
284: { 0x11, 0, "FP_ASSIST",
285: "Number of floating-point exception cases handled by microcode." },
286: { 0x12, 0, "MUL",
287: "Number of multiplies." },
288: { 0x13, 0, "DIV",
289: "Number of divides." },
290: { 0x14, 0, "CYCLES_DIV_BUSY",
291: "Number of cycles during which the divider is busy." },
292: { 0x18, 0, "IDLE_DURING_DIV",
293: "Cycles the divider is busy and all other execution units are idle." },
1.3 ! mikeb 294: { 0x19, CFL_UM, "DELAYED_BYPASS",
1.1 deraadt 295: "Delayed bypass to FP operation." },
1.3 ! mikeb 296: { 0x21, CFL_UM, "L2_ADS",
1.1 deraadt 297: "Number of L2 address strobes." },
1.3 ! mikeb 298: { 0x22, CFL_UM, "DBUS_BUSY",
! 299: "Number of cycles during which the data bus was busy." },
! 300: { 0x23, CFL_UM, "DBUS_BUSY_RD",
1.1 deraadt 301: "Number of cycles during which the data bus was busy transferring "
302: "data from L2 to the core."},
1.3 ! mikeb 303: { 0x24, CFL_UM, "L2_LINES_IN",
1.1 deraadt 304: "Number of lines allocated in the L2 (L2 cache misses.)" },
1.3 ! mikeb 305: { 0x25, CFL_UM, "L2_M_LINES_IN",
1.1 deraadt 306: "Number of modified lines allocated in the L2." },
1.3 ! mikeb 307: { 0x26, CFL_UM, "L2_LINES_OUT",
1.1 deraadt 308: "Number of lines removed from the L2 for any reason." },
1.3 ! mikeb 309: { 0x27, CFL_UM, "L2_M_LINES_OUT",
1.1 deraadt 310: "Number of modified lines removed from the L2 for any reason." },
311: { 0x28, CFL_MESI, "L2_IFETCH",
312: "Number of L2 instruction fetches." },
313: { 0x29, CFL_MESI, "L2_LD",
314: "Number of L2 data loads." },
315: { 0x2a, CFL_MESI, "L2_ST",
316: "Number of L2 data stores." },
317: { 0x2e, CFL_MESI, "L2_RQSTS",
318: "Number of L2 requests." },
319: { 0x30, CFL_MESI, "L2_REJECT_CYCLES",
320: "Number of cycles L2 is busy and rejecting new requests." },
321: { 0x32, CFL_MESI, "L2_NO_REQUEST_CYCLES",
322: "Number of cycles there is no request to access L2." },
323: { 0x3a, 0, "EST_TRANS_ALL",
324: "Number of any Intel Enhanced SpeedStep Technology transitions." },
1.3 ! mikeb 325: { 0x3b, CFL_ED|CFL_UM, "THERMAL_TRIP",
1.1 deraadt 326: "Duration in a thermal trip based on the current core clock." },
1.3 ! mikeb 327: { 0x3c, CFL_UM, "CPU_CLK_UNHALTED",
! 328: "Number of non-halted cycles." },
! 329: { 0x40, CFL_MESI, "DCACHE_LD",
1.1 deraadt 330: "L1 cacheable data reads." },
1.3 ! mikeb 331: { 0x41, CFL_MESI, "DCACHE_ST",
1.1 deraadt 332: "L1 cacheable data writes." },
1.3 ! mikeb 333: { 0x42, CFL_MESI, "DCACHE_LOCK",
1.1 deraadt 334: "L1 data cacheable locked reads." },
1.3 ! mikeb 335: { 0x43, CFL_UM, "DATA_MEM_REF",
! 336: "All memory references to the L1 DCACHE." },
! 337: { 0x44, CFL_UM, "DATA_MEM_CACHE_REF",
! 338: "All cacheable memory references to the L1 DCACHE." },
! 339: { 0x45, CFL_UM, "DCACHE_REPL",
1.1 deraadt 340: "Total lines allocated in the L1 DCACHE." },
1.3 ! mikeb 341: { 0x46, 0, "DCACHE_M_REPL",
1.1 deraadt 342: "Number of M state lines allocated in the L1 DCACHE." },
1.3 ! mikeb 343: { 0x47, 0, "DCACHE_M_EVICT",
! 344: "Number of M state lines evicted from the L1 DCACHE." },
! 345: { 0x48, 0, "DCACHE_PEND_MISS",
1.1 deraadt 346: "Total number of outstanding L1 data cache misses at any cycle." },
1.3 ! mikeb 347: { 0x49, CFL_UM, "DTLB_MISS",
1.1 deraadt 348: "Number of data references that missed TLB." },
349: { 0x4b, 0, "SSE_PRE_MISS",
350: "Number of cache misses by the SSE Prefetch NTA instructions." },
351: { 0x4c, 0, "LOAD_HIT_PRE",
352: "Load operations conflicting with a software prefetch." },
1.3 ! mikeb 353: { 0x4e, CFL_UM, "L1D_PREFETCH",
1.1 deraadt 354: "L1 DCACHE prefetch requests" },
355: { 0x4f, 0, "L1_PREF_REQ",
356: "Number of L1 prefetch requests due to DCU cache misse.s" },
1.3 ! mikeb 357: { 0x60, CFL_SA|CFL_UM, "BUS_REQ_OUTSTANDING",
1.1 deraadt 358: "Number of bus requests outstanding." },
359: { 0x61, CFL_SA, "BUS_BNR_DRV",
360: "Number of bus clock cycles during which the processor is "
361: "driving the BNR pin." },
362: { 0x62, CFL_SA, "BUS_DRDY_CLOCKS",
363: "Number of clocks during which DRDY is asserted." },
1.3 ! mikeb 364: { 0x63, CFL_SA|CFL_UM, "BUS_LOCK_CLOCKS",
1.1 deraadt 365: "Number of clocks during which LOCK is asserted." },
1.3 ! mikeb 366: { 0x64, CFL_UM, "BUS_DATA_RCV",
1.1 deraadt 367: "Number of bus clock cycles during which the processor is "
368: "receiving data." },
1.3 ! mikeb 369: { 0x65, CFL_SA|CFL_UM, "BUS_TRAN_BRD",
1.1 deraadt 370: "Number of burst read transactions." },
1.3 ! mikeb 371: { 0x66, CFL_SA|CFL_UM, "BUS_TRAN_RFO",
1.1 deraadt 372: "Number of read for ownership transactions." },
1.3 ! mikeb 373: { 0x67, CFL_SA|CFL_UM, "BUS_TRANS_WB",
1.1 deraadt 374: "Number of write back transactions." },
1.3 ! mikeb 375: { 0x68, CFL_SA|CFL_UM, "BUS_TRAN_IFETCH",
1.1 deraadt 376: "Number of instruction fetch transactions." },
1.3 ! mikeb 377: { 0x69, CFL_SA|CFL_UM, "BUS_TRAN_INVAL",
1.1 deraadt 378: "Number of invalidate transactions." },
1.3 ! mikeb 379: { 0x6a, CFL_SA|CFL_UM, "BUS_TRAN_PWR",
1.1 deraadt 380: "Number of partial write transactions." },
1.3 ! mikeb 381: { 0x6b, CFL_SA|CFL_UM, "BUS_TRANS_P",
1.1 deraadt 382: "Number of partial transactions." },
1.3 ! mikeb 383: { 0x6c, CFL_SA|CFL_UM, "BUS_TRANS_IO",
1.1 deraadt 384: "Number of I/O transactions." },
1.3 ! mikeb 385: { 0x6d, CFL_SA|CFL_UM, "BUS_TRAN_DEF",
1.1 deraadt 386: "Number of deferred transactions." },
1.3 ! mikeb 387: { 0x6e, CFL_SA|CFL_UM, "BUS_TRAN_BURST",
1.1 deraadt 388: "Number of burst transactions." },
1.3 ! mikeb 389: { 0x6f, CFL_SA|CFL_UM, "BUS_TRAN_MEM",
1.1 deraadt 390: "Number of memory transactions." },
1.3 ! mikeb 391: { 0x70, CFL_SA|CFL_UM, "BUS_TRAN_ANY",
1.1 deraadt 392: "Number of all transactions." },
393: { 0x77, CFL_MESI, "BUS_SNOOPS",
394: "Number of external bus cycles while bus lock signal asserted." },
1.3 ! mikeb 395: { 0x78, CFL_UM, "DCU_SNOOP_TO_SHARE",
! 396: "Number of DCU snoops to share-state L1 cache line due to "
! 397: "L1 misses." },
1.1 deraadt 398: { 0x7a, CFL_SA, "BUS_HIT_DRV",
399: "Number of bus clock cycles during which the processor is "
400: "driving the HIT pin." },
401: { 0x7b, CFL_SA, "BUS_HITM_DRV",
402: "Number of bus clock cycles during which the processor is "
403: "driving the HITM pin." },
404: { 0x7d, CFL_SA, "BUS_NOT_IN_USE",
405: "Number of cycles there is no transaction from the core." },
1.3 ! mikeb 406: { 0x7e, 0, "BUS_SNOOP_STALL",
1.1 deraadt 407: "Number of clock cycles during which the bus is snoop stalled." },
1.3 ! mikeb 408: { 0x7f, CFL_UM, "BUS_IO_WAIT",
1.1 deraadt 409: "Number of cycles during which IO requests wait int the bus queue." },
1.3 ! mikeb 410: { 0x80, 0, "ICACHE_READS",
1.1 deraadt 411: "Number of instruction fetches, both cacheable and non-cacheable." },
1.3 ! mikeb 412: { 0x81, 0, "ICACHE_MISSES",
1.1 deraadt 413: "Number of instruction fetch misses." },
1.3 ! mikeb 414: { 0x82, CFL_UM, "ITLB_MISS",
1.1 deraadt 415: "Number of ITLB misses." },
1.3 ! mikeb 416: { 0x83, CFL_UM, "INSQ_QUEUE",
1.1 deraadt 417: "Cycles during which the instruction queue is full." },
1.3 ! mikeb 418: { 0x85, CFL_UM, "ITLB_MISSES",
1.1 deraadt 419: "Number of ITLB misses." },
1.3 ! mikeb 420: { 0x86, 0, "IFU_MEM_STALL",
! 421: "Number of cycles when the instruction fetches stalled." },
1.1 deraadt 422: { 0x87, 0, "ILD_STALL",
423: "Number of cycles that the instruction length decoder is stalled." },
424: { 0x88, 0, "BR_INST_EXEC",
425: "Number of branch instructions executed." },
426: { 0x89, 0, "BR_MISSP_EXEC",
427: "Number of mispredicted branch instructions that were executed." },
428: { 0x8a, 0, "BR_BAC_MISSP_EXEC",
429: "Number of branch instructions that were mispredicted at decoding." },
430: { 0x8b, 0, "BR_CND_EXEC",
431: "Number of conditional branch instructions executed, but not "
432: "necessarily retired." },
433: { 0x8c, 0, "BR_CND_MISSP_EXEC",
434: "Number of mispredicted conditional branch instructions that "
435: "were executed." },
436: { 0x8d, 0, "BR_IND_EXEC",
437: "Number of indirect branch instructions that were executed." },
438: { 0x8e, 0, "BR_IND_MISSP_EXEC",
439: "number of mispredicted indirect branch instructions that were "
440: "executed." },
441: { 0x8f, 0, "BR_RET_EXEC",
442: "Number of RET instructions that were executed." },
443: { 0x90, 0, "BR_RET_MISSP_EXEC",
444: "Number of mispredicted RET instructions that were executed." },
445: { 0x91, 0, "BR_RET_BAC_MISSP_EXEC",
446: "Number of RET instructions that were executed and were mispredicted "
447: "at decoding." },
448: { 0x92, 0, "BR_CALL_EXEC",
449: "Number of CALL instructions executed." },
450: { 0x93, 0, "BR_CALL_MISSP_EXEC",
451: "Number of mispredicted CALL instructions that were executed." },
452: { 0x94, 0, "BR_IND_CALL_EXEC",
453: "Number of indirect CALL instructions that were executed." },
454: { 0x97, 0, "BR_TKN_BUBBLE_1",
455: "Number of times a taken branch predicted taken with bubble 1." },
456: { 0x98, 0, "BR_TKN_BUBBLE_2",
457: "Number of times a taken branch predicted taken with bubble 2." },
458: { 0xa0, 0, "RS_UOPS_DISPATCHED",
459: "Number of microops dispatched for execution." },
1.3 ! mikeb 460: { 0xa1, CFL_UM, "RS_UOPS_DISPATCHED",
! 461: "Number of cycles for which micro-ops dispatched for execution." },
1.1 deraadt 462: { 0xa2, 0, "RESOURCE_STALL",
463: "Number of cycles while there us a resource related stall." },
1.3 ! mikeb 464: { 0xaa, CFL_UM, "MACRO_INSTS",
1.1 deraadt 465: "Number of instructions decoded (but not necessarily executed "
466: "or retired)." },
1.3 ! mikeb 467: { 0xab, CFL_UM, "ESP",
1.1 deraadt 468: "ESP register operations." },
469: { 0xb0, 0, "SIMD_UOPS_EXEC",
470: "Number of SIMD micro-ops executed (excluding stores)." },
471: { 0xb1, 0, "SIMD_SAT_UOP_EXEC",
472: "Number of SIMD saturated arithmetic micro-ops executed." },
1.3 ! mikeb 473: { 0xb3, CFL_UM, "SIMD_INT",
! 474: "Number of SIMD integer instructions executed." },
! 475: { 0xc0, 0, "INST_RET",
1.1 deraadt 476: "Number of instructions retired." },
1.3 ! mikeb 477: { 0xc1, 0, "FP_COMP_INSTR_RET",
1.1 deraadt 478: "Number of computational floating-point operations retired." },
1.3 ! mikeb 479: { 0xc2, 0, "UOPS_RET",
1.1 deraadt 480: "Number of UOPs retired." },
1.3 ! mikeb 481: { 0xc3, 0, "SMC_DETECTED",
! 482: "Number of times self-modifying code condition detected." },
! 483: { 0xc4, 0, "BR_INST_RET",
1.1 deraadt 484: "Number of branch instructions retired." },
1.3 ! mikeb 485: { 0xc5, 0, "BR_MISPRED_RET",
1.1 deraadt 486: "Number of mispredicted branches retired." },
487: { 0xc6, 0, "CYCLES_INT_MASKED",
1.3 ! mikeb 488: "Number of cycles for which interrupts are disabled." },
! 489: { 0xc7, 0, "CYCLES_INT_PENDING_MASKED",
! 490: "Number of cycles for which interrupts are disabled "
! 491: "and interrupts are pending." },
! 492: { 0xc8, 0, "HW_INT_RX",
1.1 deraadt 493: "Number of hardware interrupts received." },
1.3 ! mikeb 494: { 0xc9, 0, "BR_TAKEN_RET",
! 495: "Number of taken branch instructions retired."},
! 496: { 0xca, 0, "BR_MISPRED_TAKEN_RET",
! 497: "Number of taken andmispredicted branch instructions retired." },
1.1 deraadt 498: { 0xcb, 0, "MEM_LOAD_RETIRED",
499: "Number of retired load operations that missed the L1 DCACHE." },
1.3 ! mikeb 500: { 0xcc, 0, "MMX_FP_TRANS",
! 501: "Number of transitions between MMX and X87." },
! 502: { 0xcd, 0, "MMX_ASSIST",
! 503: "Number of EMMS executed." },
! 504: { 0xce, 0, "MMX_INSTR_RET",
! 505: "Number of MMX instructions retired." },
! 506: { 0xcf, 0, "MMX_SAT_INSTR_RET",
! 507: "Number of MMX saturated arithmetic instructions retired." },
1.1 deraadt 508: { 0xd0, 0, "INSTR_DECODED",
509: "Number of instructions decoded." },
1.3 ! mikeb 510: { 0xd2, CFL_UM, "RAT_STALLS",
1.1 deraadt 511: "Number of cycles or events for partial stalls." },
1.3 ! mikeb 512: { 0xd4, CFL_UM, "SEG_RENAME_STALLS",
1.1 deraadt 513: "Number of stalls due to the lack of renaming resources." },
1.3 ! mikeb 514: { 0xd5, CFL_UM, "SEG_REG_RENAMES",
1.1 deraadt 515: "Number of times the segment register is renamed." },
516: { 0xd7, 0, "ESP_UOPS",
517: "Number of ESP folding instruction decoded." },
518: { 0xd8, 0, "SIMD_FD_RET",
519: "Number of SSE/SSE2 instructions retired." },
520: { 0xd9, 0, "SIMD_FP_COM_RET",
521: "Number of SSE/SSE2 compute instructions retired." },
522: { 0xda, 0, "FUSED_UOPS_RET",
523: "Number of all fused uops retired." },
524: { 0xdb, 0, "UNFUSION",
525: "Number of all unfusion events in the ROB." },
1.3 ! mikeb 526: { 0xdc, CFL_UM, "RESOURCE_STALLS",
1.1 deraadt 527: "Number of cycles when the number of instructions in the pipeline "
528: "waiting for retirement reaches the limit the processor can handle." },
529: { 0xe0, 0, "BR_INST_DECODED",
530: "Number of branch instructions decoded." },
531: { 0xe2, 0, "BTB_MISSES",
532: "Number of branches the BTB did not produce a prediction." },
533: { 0xe4, 0, "BOGUS_BR",
534: "Number of byte sequences that were mistakenly detected as taken "
535: "branch instructions." },
536: { 0xe6, 0, "BACLEARS",
537: "Number of times BACLEAR is asserted." },
538: { 0xf0, 0, "PREF_RQSTS_UP",
539: "Number of upward prefetches issued from the Data Prefetch Logic "
540: "(DPL) to the L2 cache." },
541: { 0xf8, 0, "PREF_RQSTS_DN",
542: "Number of downward prefetches issued from the Data Prefetch Logic "
543: "(DPL) to the L2 cache." },
544: { 0x0, 0, NULL, NULL }
545: };
546:
547: struct ctrfn amdfn[] = {
548: { 0x00, 0, "Dispatched FPU operations", NULL },
549: { 0x01, 0, "Cycles with no FPU ops retired", NULL },
550: { 0x02, 0, "Dispatched fast flag FPU operations", NULL },
551: { 0x20, 0, "Segment register loads", NULL },
552: { 0x21, 0, "Pipeline restart due to self-modifying code", NULL },
553: { 0x22, 0, "Pipeline restart due to probe hit", NULL },
554: { 0x23, 0, "LS2 buffer is full", NULL },
555: { 0x24, 0, "Locked operations", NULL },
556: { 0x26, 0, "Retired CFLUSH instructions", NULL },
557: { 0x27, 0, "Retired CPUID instructions", NULL },
558: { 0x40, 0, "Data cache accesses", NULL },
559: { 0x41, 0, "Data cache misses", NULL },
560: { 0x42, 0, "Data cache refills from L2 or system", NULL },
561: { 0x43, 0, "Data cache refills from system", NULL },
562: { 0x44, 0, "Data cache lines evicted", NULL },
563: { 0x45, 0, "L1 DTLB miss and L2 DTLB hit", NULL },
564: { 0x46, 0, "L1 DTLB miss and L2 DTLB miss", NULL },
565: { 0x47, 0, "Misaligned access", NULL },
566: { 0x48, 0, "Microarchitectural late cancel of an access", NULL },
567: { 0x49, 0, "Microarchitectural early cancel of an access", NULL },
568: { 0x4a, 0, "Single bit ECC errors recorded by scrubber", NULL },
569: { 0x4b, 0, "Prefetch instructions dispatched", NULL },
570: { 0x4c, 0, "DCACHE misses by locked instructions", NULL },
571: { 0x65, 0, "Memory requests by type", NULL },
572: { 0x67, 0, "Data prefetcher", NULL },
573: { 0x6c, 0, "System read responses by coherency state", NULL },
574: { 0x6d, 0, "Quadwords written to system", NULL },
575: { 0x76, 0, "CPU clocks not halted", NULL },
576: { 0x7d, 0, "Requests to L2 cache", NULL },
577: { 0x7e, 0, "L2 cache misses", NULL },
578: { 0x7f, 0, "L2 cache fill/writeback", NULL },
579: { 0x80, 0, "ICACHE fetches", NULL },
580: { 0x81, 0, "ICACHE misses", NULL },
581: { 0x82, 0, "ICACHE refills from L2", NULL },
582: { 0x83, 0, "ICACHE refills from system", NULL },
583: { 0x84, 0, "L1 ITLB miss and L2 ITLB hit", NULL },
584: { 0x85, 0, "L1 ITLB miss and L2 ITLB miss", NULL },
585: { 0x86, 0, "Pipeline restart due to instruction stream probe", NULL },
586: { 0x87, 0, "Instruction fetch stall", NULL },
587: { 0x88, 0, "Return stack hits", NULL },
588: { 0x89, 0, "Return stack overflows", NULL },
589: { 0xc0, 0, "Retired instructions", NULL },
590: { 0xc1, 0, "Retired microops", NULL },
591: { 0xc2, 0, "Retired branch instructions", NULL },
592: { 0xc3, 0, "Retired mispredicted branch instructions", NULL },
593: { 0xc4, 0, "Retired taken branch instructions", NULL },
594: { 0xc5, 0, "Retired mispredicted taken branch instructions", NULL },
595: { 0xc6, 0, "Retired far control transfers", NULL },
596: { 0xc7, 0, "Retired branch resyncs", NULL },
597: { 0xc8, 0, "Retired near returns", NULL },
598: { 0xc9, 0, "Retired mispredicted near returns", NULL },
599: { 0xca, 0, "Retired mispredicted indirect brnaches", NULL },
600: { 0xcb, 0, "Retired MMX/FP instructions", NULL },
601: { 0xcc, 0, "Retired fastpath double op instructions", NULL },
602: { 0xcd, 0, "Interrupts-masked cycles", NULL },
603: { 0xce, 0, "Interrupts-masked cycles with interrupts pending", NULL },
604: { 0xcf, 0, "Interrupts taken", NULL },
605: { 0xd0, 0, "Decoder empty", NULL },
606: { 0xd1, 0, "Dispatch stalls", NULL },
607: { 0xd2, 0, "Dispatch stalls for branch abort retire", NULL },
608: { 0xd3, 0, "Dispatch stalls for serialisation", NULL },
609: { 0xd4, 0, "Dispatch stalls for segment load", NULL },
610: { 0xd5, 0, "Dispatch stalls for reoder buffer full", NULL },
611: { 0xd6, 0, "Dispatch stalls for reservation station full", NULL },
612: { 0xd7, 0, "Dispatch stalls for FPU full", NULL },
613: { 0xd8, 0, "Dispatch stalls for LS full", NULL },
614: { 0xd9, 0, "Dispatch stalls waiting for all quite", NULL },
615: { 0xda, 0, "Dispatch stalls for far transfer or resync to retire", NULL },
616: { 0xdb, 0, "FPU exceptions", NULL },
617: { 0xdc, 0, "DR0 breakpoint matches", NULL },
618: { 0xdd, 0, "DR1 breakpoint matches", NULL },
619: { 0xde, 0, "DR2 breakpoint matches", NULL },
620: { 0xdf, 0, "DR3 breakpoint matches", NULL },
621: { 0xe0, 0, "DRAM accesses", NULL },
622: { 0xe1, 0, "Memory controller page tables overflow", NULL },
623: { 0xe3, 0, "Memory controller turnarounds", NULL },
624: { 0xe4, 0, "Memory controller bypass counter saturation", NULL },
625: { 0xe5, 0, "Sized blocks", NULL },
626: { 0xe8, 0, "ECC errors", NULL },
627: { 0xe9, 0, "CPU/IO requests to memory/IO", NULL },
628: { 0xea, 0, "Cache blocks commands", NULL },
629: { 0xeb, 0, "Sized commands", NULL },
630: { 0xec, 0, "Probe responses and upstream requests", NULL },
631: { 0xee, 0, "GART events", NULL },
632: { 0xf6, 0, "HT link 0 transmit bandwidth", NULL },
633: { 0xf7, 0, "HT link 1 transmit bandwidth", NULL },
634: { 0xf8, 0, "HT link 2 transmit bandwidth", NULL },
635: { 0x0, 0, NULL, NULL }
636: };
637:
638: #endif /* _PCTRVAR_H_ */
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