===================================================================
RCS file: /cvsrepo/anoncvs/cvs/www/72.html,v
retrieving revision 1.69
retrieving revision 1.70
diff -c -r1.69 -r1.70
*** www/72.html 2022/10/22 12:28:14 1.69
--- www/72.html 2022/10/23 01:50:46 1.70
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*** 627,633 ****
use non-standard UARTs on the AMD Ryzen Embedded V1000 SoCs as console.
Switched bootloaders to the extended BOOTARG_CONSDEV struct.
Added UFS2 support to landisk boot blocks.
! Removed "force CHS" capabilty from biosboot(8)
Security improvements:
--- 627,633 ----
use non-standard UARTs on the AMD Ryzen Embedded V1000 SoCs as console.
Switched bootloaders to the extended BOOTARG_CONSDEV struct.
Added UFS2 support to landisk boot blocks.
! Removed "force CHS" capability from biosboot(8)
Security improvements:
***************
*** 1062,1068 ****
Increment the input and output position for EVP AES CFB1.
Ensure there is no trailing data for a CCS received by the
TLSv1.3 stack.
! Use CBS when procesing a CCS message in the legacy stack.
Be stricter with middlebox compatibility mode in the TLSv1.3
server.
--- 1062,1068 ----
Increment the input and output position for EVP AES CFB1.
Ensure there is no trailing data for a CCS received by the
TLSv1.3 stack.
! Use CBS when processing a CCS message in the legacy stack.
Be stricter with middlebox compatibility mode in the TLSv1.3
server.