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version 1.68, 2007/11/03 12:34:40 version 1.69, 2007/11/12 21:47:37
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 With the help of Mark Kettenis, the toolchain effort eventually produced  With the help of Mark Kettenis, the toolchain effort eventually produced
 working binutils and gdb in late may 2004.  working binutils and gdb in late may 2004.
   
   <p>
   Work towards multiprocessor support on the MVME188 boards started in
   summer 2005 and, after a lot of tedious bugfixing, was eventually
   completed shortly after the 4.2 release in november 2007.
   
 <hr>  <hr>
 <a name="status"></a>  <a name="status"></a>
 <h3><font color="#0000e0"><strong>Current status:</strong></font></h3>  <h3><font color="#0000e0"><strong>Current status:</strong></font></h3>
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 <li><strong>MVME188 and MVME188A</strong><br>  <li><strong>MVME188 and MVME188A</strong><br>
 Contrary to the other MVME processor boards, this board has no on-board  Contrary to the other MVME processor boards, this board has no on-board
 devices; it just acts as a container for an <i>HYPERmodule</i> which provides  devices; it just acts as a container for an <i>HYPERmodule</i> which provides
 one, two or four 88110 processors, and two or four 88200 (16KB cache) or 88204  one, two or four 88100 processors, and two or four 88200 (16KB cache) or 88204
 (64KB cache) CMMUs per processor.<br>  (64KB cache) CMMUs per processor.<br>
 All HYPERmodules combinations are supported, but M88200 1P128 and 1P512 have  All HYPERmodules combinations are supported, but M88200 1P128 and 1P512 have
 not been tested.<br>  not been tested.<br>
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 An entry-level design similar to the MVME187, but based on the 88110 processor  An entry-level design similar to the MVME187, but based on the 88110 processor
 with integrated MMU and cache controller.  with integrated MMU and cache controller.
 <li><strong>MVME197SP and MVME197DP</strong><br>  <li><strong>MVME197SP and MVME197DP</strong><br>
 Improved versions of the MVME197LE, with one or two 88110 processors, and  Improved versions of the MVME197LE, with one (SP) or two (DP) 88110 processors,
 one 88410 external cache controller per processor.  and one 88410 external cache controller per processor.
 </ul>  </ul>
   
 <hr>  <hr>
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