[BACK]Return to plus.html CVS log [TXT][DIR] Up to [local] / www

Diff for /www/plus.html between version 1.1438 and 1.1439

version 1.1438, 2019/05/08 23:10:43 version 1.1439, 2019/05/09 06:15:14
Line 94 
Line 94 
 <li>Ensured <a href="https://man.openbsd.org/mcx">mcx(4)</a> completion queues are always rearmed to prevent rx or tx completion stalling.  <li>Ensured <a href="https://man.openbsd.org/mcx">mcx(4)</a> completion queues are always rearmed to prevent rx or tx completion stalling.
 <!-- 2019/05/06 -->  <!-- 2019/05/06 -->
 <li>Adjusted <a href="https://man.openbsd.org/unwind">unwind(8)</a> to try to resolve the DNSSEC trust anchor only if we have a validating resolver context.  <li>Adjusted <a href="https://man.openbsd.org/unwind">unwind(8)</a> to try to resolve the DNSSEC trust anchor only if we have a validating resolver context.
 <li>To restore <a href="https://man.openbsd.org/lockf">lockf(3)</a> detection, introduced a list for all pending blocked locks to be scanned before waiting on a blocking lock in order to determine whether sleeping would cause a deadlock.  <li>To restore <a href="https://man.openbsd.org/lockf">lockf(3)</a> deadlock detection, introduced a list for all pending blocked locks to be scanned before waiting on a blocking lock in order to determine whether sleeping would cause a deadlock.
 <li>Enforced store/load order when setting or clearing AST flag on mips64, preventing an unlikely case with inter-CPU ASTs where the receiving CPU uses stale state. Ensured that the clearing store is performed before other memory accesses, preventing potential loss of an AST request.  <li>Enforced store/load order when setting or clearing AST flag on mips64, preventing an unlikely case with inter-CPU ASTs where the receiving CPU uses stale state. Ensured that the clearing store is performed before other memory accesses, preventing potential loss of an AST request.
 <li>Issued a write-write barrier before sending IPI on mips64, preventing a receiving CPU from observing an old state when processing the interrupt.  <li>Issued a write-write barrier before sending IPI on mips64, preventing a receiving CPU from observing an old state when processing the interrupt.
 <li>Made the interrupt and trap return paths check for ASTs with interrupts disabled, fixing unintentional delay of ASTs on MP mips64.  <li>Made the interrupt and trap return paths check for ASTs with interrupts disabled, fixing unintentional delay of ASTs on MP mips64.
Legend:
Removed from v.1.1438  
changed lines
  Added in v.1.1439