version 1.134, 2003/04/14 00:41:22 |
version 1.135, 2003/04/25 13:07:29 |
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<li>SM71: 75 MHz SuperSPARC with 1MB of secondary cache |
<li>SM71: 75 MHz SuperSPARC with 1MB of secondary cache |
<li>SM81: 85 MHz SuperSPARC with 1MB of secondary cache |
<li>SM81: 85 MHz SuperSPARC with 1MB of secondary cache |
<li>SM81-2: 85 MHz SuperSPARC with 2MB of secondary cache |
<li>SM81-2: 85 MHz SuperSPARC with 2MB of secondary cache |
<li>SM100: dual 40 MHz Cypress 7C601 with 64KB of primary cache |
<li>SM100: dual 40 MHz Cypress 7C605 with 64KB of primary cache |
<li>Ross HyperSparc RT620/RT625 at 90MHz, with 256KB of primary cache |
<li>Ross HyperSparc RT620/RT625 at 90MHz, with 256KB of primary cache |
<li>Ross HyperSparc RT620/RT625 at 125MHz, with 256KB of primary cache |
<li>Ross HyperSparc RT620/RT625 at 125MHz, with 256KB of primary cache |
<li>Ross HyperSparc RT620/RT625 at 150MHz, with 512KB of primary cache |
<li>Ross HyperSparc RT620/RT625 at 150MHz, with 512KB of primary cache |
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<a href="sparc64.html">OpenBSD/sparc64</a> port. |
<a href="sparc64.html">OpenBSD/sparc64</a> port. |
<li>Solbourne machines: these machines are quite different, and some are |
<li>Solbourne machines: these machines are quite different, and some are |
plagued by processor bugs. |
plagued by processor bugs. |
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<li>Tadpole SPARCbook 1, LC and 2: these machines use quite unusual components, |
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and do not have a Sun-compatible PROM. |
</ul> |
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