version 1.76, 2000/02/21 17:10:17 |
version 1.77, 2000/02/21 17:32:52 |
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variety of sparc processor and cache implementations along with their |
variety of sparc processor and cache implementations along with their |
undocumented bugs, rather then general kernel problems. |
undocumented bugs, rather then general kernel problems. |
Feedback on which models do and do not work reliably is |
Feedback on which models do and do not work reliably is |
appreciated, particularly with the newer sun4m implementations like the |
appreciated, particularly with newer models or upgrades. |
Fujitsu TurboSparc and Ross HyperSparc based systems and upgrades. |
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</p> |
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<p> |
<p> |
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with SBUS and VME busses. |
with SBUS and VME busses. |
<li>LC: 50MHz MicroSPARC-1 based machines (aka Classic) |
<li>LC: 50MHz MicroSPARC-1 based machines (aka Classic) |
<li>LX: LC with a few more devices |
<li>LX: LC with a few more devices |
<li>SS5: MicroSPARC-2 based machines available in 60, 70, |
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85, 110, and 170 MHz versions |
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<li>SS4: Reduced cost version of the SS5, available at 70MHz and 110MHz |
<li>SS4: Reduced cost version of the SS5, available at 70MHz and 110MHz |
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<li>SS5: MicroSPARC-2 based machines available in 60, 70, 85, |
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and 110 MHz versions |
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<li>SS5: TurboSPARC cpus in accelerated SS5 machines, running at 170 MHz |
<li>SS10: Pizzabox <a href=#mbus>mbus</a>-based machine |
<li>SS10: Pizzabox <a href=#mbus>mbus</a>-based machine |
<li>SS20: Improved Pizzabox <a href=#mbus>mbus</a>-based machine |
<li>SS20: Improved Pizzabox <a href=#mbus>mbus</a>-based machine |
<li>Sun Voyager (untested) |
<li>Sun Voyager (untested) |
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<a name=mbus></a> |
<a name=mbus></a> |
<li><strong> Mbus CPU modules</strong> |
<li><strong> Mbus CPU modules</strong> |
<ul> |
<ul> |
<li> SM30 |
<li> SM30: 30 or 36 MHz Supersparc with no secondary cache |
<li> SM41: 40 MHz SuperSPARC |
<li> SM40: 40 MHz SuperSPARC with no secondary cache |
<li> SM51: 50 MHz SuperSPARC with 1MB of secondary cache |
<li> SM41: 40 MHz SuperSPARC with 1MB of secondary cache |
<li> SM61: 60 MHz SuperSPARC with 1MB of secondary cache |
<li> SM50: 50 MHz SuperSPARC with no seconary cache |
<li> SM71: 75 MHz SuperSPARC with 1MB of secondary cache |
<li> SM51: 50 MHz SuperSPARC with 1MB of secondary cache |
<li> SM81: 85 MHz SuperSPARC with 1MB of secondary cache |
<li> SM51-2: 50 MHz SuperSPARC with 2MB of secondary cache |
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<li> SM61: 60 MHz SuperSPARC with 1MB of secondary cache |
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<li> SM61-2: 60 MHz SuperSPARC with 2MB of secondary cache |
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<li> SM71: 75 MHz SuperSPARC with 1MB of secondary cache |
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<li> SM81: 85 MHz SuperSPARC with 1MB of secondary cache |
<li> SM81-2: 85 MHz SuperSPARC with 2MB of secondary cache |
<li> SM81-2: 85 MHz SuperSPARC with 2MB of secondary cache |
<li> SM100: 40 MHz Cypress 7C601 |
<li> SM100: dual 40 MHz Cypress 7C601 with 64KB of primary cache |
<li> Ross HyperSparc processor modules |
<li> Ross HyperSparc RT620/RT625 at 125MHz, with 256KB of primary cache |
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<li> Ross HyperSparc RT620/RT625 at 150MHz, with 512KB of primary cache |
</ul> |
</ul> |
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<p> |
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<li><strong> Sun keyboard and mouse</strong> |
<li><strong> Sun keyboard and mouse</strong> |
<ul> |
<ul> |
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<h4>OpenBSD/sparc does *not* run on these machines (yet):</h4> |
<h4>OpenBSD/sparc does *not* run on these machines (yet):</h4> |
<ul> |
<ul> |
<li> sun4: 4/400 (lacks support for the I/O cache, and has Ethernet problems) |
<li> sun4: 4/400 (lacks support for the I/O cache, and has Ethernet problems) |
<li> sun4m: older systems with Viking (TMS390Z55) processor modules |
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without external cache chips, aka SuperCache, aka MXCC, aka PAC. |
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<li> sun4d machines<br> |
<li> sun4d machines<br> |
SPARC Server 1000<br> |
SPARC Server 1000<br> |
SPARC Center 2000<br> |
SPARC Center 2000<br> |
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not support that yet. |
not support that yet. |
<li> sun4u (<a href="sparc64.html">sparc64</a>): UltraSPARC 64-bit machines. |
<li> sun4u (<a href="sparc64.html">sparc64</a>): UltraSPARC 64-bit machines. |
<li> It does not work on most Solbourne machines, which are quite different. |
<li> It does not work on most Solbourne machines, which are quite different. |
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(However, it works on the sun4c/sun4m compatible machines.) |
</ul> |
</ul> |
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<p> |
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OpenBSD/sparc on the 4c/4m machines is critically dependent on configuration |
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information returned by the OpenBoot PROM. A sparc clone that differs |
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substantially from the Sun model as far as device names and properties will |
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require additional work in this area. |
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<h4>Unsupported Devices. First of all, there are MANY unsupported devices. |
<h4>Unsupported Devices. First of all, there are MANY unsupported devices. |
A comprehensive list can probably not be written.</h4> |
A comprehensive list can probably not be written.</h4> |
<ul> |
<ul> |
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HME part of the card. |
HME part of the card. |
<p> |
<p> |
<li><strong>SBUS FDDI cards</strong><br> |
<li><strong>SBUS FDDI cards</strong><br> |
We are trying to get documentation from NPIX (who built the card for Sun). |
We are trying to get documentation from <a href=www.npix.com>NPI</a> |
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(who built the card for Sun). |
<p> |
<p> |
<li><strong>Tadpole PCMCIA bridge</strong> |
<li><strong>Tadpole PCMCIA bridge</strong> |
<p> |
<p> |