===================================================================
RCS file: /cvsrepo/anoncvs/cvs/www/sparc.html,v
retrieving revision 1.76
retrieving revision 1.77
diff -u -r1.76 -r1.77
--- www/sparc.html	2000/02/21 17:10:17	1.76
+++ www/sparc.html	2000/02/21 17:32:52	1.77
@@ -125,8 +125,7 @@
 variety of sparc processor and cache implementations along with their
 undocumented bugs, rather then general kernel problems.
 Feedback on which models do and do not work reliably is
-appreciated, particularly with the newer sun4m implementations like the
-Fujitsu TurboSparc and Ross HyperSparc based systems and upgrades.
+appreciated, particularly with newer models or upgrades.
 </p>
 
 <p>
@@ -183,9 +182,10 @@
 	    with SBUS and VME busses.
 	<li>LC: 50MHz MicroSPARC-1 based machines (aka Classic)
 	<li>LX: LC with a few more devices
-	<li>SS5: MicroSPARC-2 based machines available in 60, 70,
-	    85, 110, and 170 MHz versions
 	<li>SS4: Reduced cost version of the SS5, available at 70MHz and 110MHz
+	<li>SS5: MicroSPARC-2 based machines available in 60, 70, 85,
+	    and 110 MHz versions
+	<li>SS5: TurboSPARC cpus in accelerated SS5 machines, running at 170 MHz
 	<li>SS10: Pizzabox <a href=#mbus>mbus</a>-based machine
 	<li>SS20: Improved Pizzabox <a href=#mbus>mbus</a>-based machine
 	<li>Sun Voyager (untested)
@@ -220,16 +220,22 @@
 <a name=mbus></a>
 <li><strong> Mbus CPU modules</strong>
   <ul>
-   <li> SM30
-   <li> SM41: 40 MHz SuperSPARC
-   <li> SM51: 50 MHz SuperSPARC with 1MB of secondary cache
-   <li> SM61: 60 MHz SuperSPARC with 1MB of secondary cache
-   <li> SM71: 75 MHz SuperSPARC with 1MB of secondary cache
-   <li> SM81: 85 MHz SuperSPARC with 1MB of secondary cache
+   <li> SM30:   30 or 36 MHz Supersparc with no secondary cache
+   <li> SM40:   40 MHz SuperSPARC with no secondary cache
+   <li> SM41:   40 MHz SuperSPARC with 1MB of secondary cache
+   <li> SM50:   50 MHz SuperSPARC with no seconary cache
+   <li> SM51:   50 MHz SuperSPARC with 1MB of secondary cache
+   <li> SM51-2: 50 MHz SuperSPARC with 2MB of secondary cache
+   <li> SM61:   60 MHz SuperSPARC with 1MB of secondary cache
+   <li> SM61-2: 60 MHz SuperSPARC with 2MB of secondary cache
+   <li> SM71:   75 MHz SuperSPARC with 1MB of secondary cache
+   <li> SM81:   85 MHz SuperSPARC with 1MB of secondary cache
    <li> SM81-2: 85 MHz SuperSPARC with 2MB of secondary cache
-   <li> SM100: 40 MHz Cypress 7C601
-   <li> Ross HyperSparc processor modules
+   <li> SM100:  dual 40 MHz Cypress 7C601 with 64KB of primary cache
+   <li> Ross HyperSparc RT620/RT625 at 125MHz, with 256KB of primary cache
+   <li> Ross HyperSparc RT620/RT625 at 150MHz, with 512KB of primary cache
   </ul>
+  <p>
 
 <li><strong> Sun keyboard and mouse</strong>
   <ul>
@@ -342,8 +348,6 @@
 <h4>OpenBSD/sparc does *not* run on these machines (yet):</h4>
 <ul>
  <li> sun4: 4/400 (lacks support for the I/O cache, and has Ethernet problems)
- <li> sun4m: older systems with Viking (TMS390Z55) processor modules
-	without external cache chips, aka SuperCache, aka MXCC, aka PAC.
  <li> sun4d machines<br>
       SPARC Server 1000<br>
       SPARC Center 2000<br>
@@ -351,14 +355,9 @@
       not support that yet.
  <li> sun4u (<a href="sparc64.html">sparc64</a>): UltraSPARC 64-bit machines.
  <li> It does not work on most Solbourne machines, which are quite different.
+      (However, it works on the sun4c/sun4m compatible machines.)
 </ul>
 
-<p>
-OpenBSD/sparc on the 4c/4m machines is critically dependent on configuration
-information returned by the OpenBoot PROM.  A sparc clone that differs
-substantially from the Sun model as far as device names and properties will
-require additional work in this area.
-
 <h4>Unsupported Devices. First of all, there are MANY unsupported devices.
 A comprehensive list can probably not be written.</h4>
 <ul>
@@ -410,7 +409,8 @@
     HME part of the card.
 <p>
 <li><strong>SBUS FDDI cards</strong><br>
-    We are trying to get documentation from NPIX (who built the card for Sun).
+    We are trying to get documentation from <a href=www.npix.com>NPI</a>
+    (who built the card for Sun).
 <p>
 <li><strong>Tadpole PCMCIA bridge</strong>
 <p>
@@ -431,7 +431,7 @@
 <a href=plat.html><img height=24 width=24 src=back.gif border=0 alt=OpenBSD></a> 
 <a href=mailto:www@openbsd.org>www@openbsd.org</a>
 <br>
-<small>$OpenBSD: sparc.html,v 1.76 2000/02/21 17:10:17 art Exp $</small>
+<small>$OpenBSD: sparc.html,v 1.77 2000/02/21 17:32:52 deraadt Exp $</small>
 
 </body>
 </html>